CMOS Process Integration

Instructor: Dr. Badih El-Kareh

Course Overview

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The question looming in everyone’s mind is “How far into the future can this continue?” CMOS Process Integration is a 2 day course that offers detailed instruction on the physics behind the operation of a modern integrated circuit, and the processing technologies required to make them. We place special emphasis on current issues related to designing and manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.

By focusing on the fundamentals of transistor operation and interconnect performance, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain how semiconductor devices work without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.

Participants learn basic but powerful aspects about the semiconductor industry. This skill-building series is divided into three segments:

1. Basic Device Operation: Participants learn the fundamentals of transistor operation. They learn why CMOS (Complimentary Metal Oxide Semiconductor) devices dominate the industry today.
2. Fabrication Technologies: Participants learn the fundamental manufacturing technologies that are used to make modern integrated circuits. They learn the typical CMOS process flows used in integrated circuit fabrication.
3. Current Issues in Process Integration: Participants learn how device operation is increasingly constrained by three parameters. They also learn about the impact of using new materials in the fabrication process and how those materials may create problems for the manufacturers in the future.
4. An Overview of Issues Related to Process Integration: Participants learn about the image of new materials, yield, reliability and scaling on technology and process integration. They receive an overview of the major reliability mechanisms that affect silicon ICs today.

Course Objectives

1. The seminar will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.
2. Participants will understand the basic concepts behind transistor operation and performance.
3. The seminar will identify the key issues related to the continued growth of the semiconductor industry.
4. The seminar offers a wide variety of sample problems that participants work to help them gain knowledge of the fundamentals of device operation and manufacturing.
5. Participants will be able to identify basic and advanced technology features on semiconductor devices. This includes features like hi-k dielectrics, strained silicon, copper, and low-k dielectrics.
6. Participants will understand how reliability, power consumption and device performance are interrelated.
7. Participants will be able to make decisions about how to construct and evaluate new CMOS technologies.

Instructional Strategy

By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor devices and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field. The handbook offers hundreds of pages of additional reference material the participants can use back at their daily activities.

Course Outline

1. Introduction
2. Conventional CMOS
1. Key Components and Parameters
2. Process Overview and Integration Issues
3. Scaling and Limitations
3. Mobility Enhancement Techniques
1. Strained Silicon
2. Crystal Orientation
4. Gate Stacks, High-k Dielectrics
1. Gate Conductor Materials and Properties
2. High-k Materials and Properties
3. Gate Stack Integration
5. Options for Source-Drain, Extensions
1. Elevated Source/Drain
2. Co-Implantation of Inactive Species
3. Schottky-Barrier Source-Drain
6. Three-Dimensional Structures
1. FinFETs, Multi-Gates
7. Interconnects
1. Aluminum Interconnects, Issues
2. Copper Interconnects, Issues
3. Low-k Dielectrics
8. CMOS Reliability Considerations
1. Electrostatic Discharge
2. Electromigration and Stress Migration
3. Soft Errors, Plasma Damage
4. Dielectric Reliability
5. Bias Temperature Instabilities
6. Hot Carrier Reliability
7. Burn-In
9. Yield Considerations
1. Yield Detractors
2. Models
3. Monitors

Dr. Badih El-Kareh, Independent Consultant

Dr. El-Kareh was previously a Process Development Manager at Texas Instruments, Dallas, developing advanced BiCMOS processes in Freising, Germany. Dr. El-Kareh also worked at IBM and has 35 years experience in semiconductor device design, process integration and characterization. This includes the implementation ofCMOS, and BiCMOS technologies and devices for memory, logic, and analog applications. He is author of a book on VLSI silicon devices and a book on modern semiconductor processing technologies. He has authored or co-authored 32 papers and has 25 patents issued. Dr. El-Kareh is a senior member of IEEE. He has 20 years experience in academic and industrial teaching.

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Doubletree Hotel San Jose
2050 Gateway Place
San Jose, CA 95110
408-453-4000

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For information on dates in Southeast Asia, email KS Chuah at ks.chuah@semitracks.com

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Last modified: 10/13/08