Design Debug Course

Instructor: Gary Woods

Course Overview

Design Debug is an increasingly difficult and complex process. Today, engineers are required to locate design problems and process variation points on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform design debug. This requires knowledge of subjects like: design, testing, technology, and even processing. Non-functional, partially functional devices, and low yields can lead to product introduction delays and idle manufacturing lines that can cost a company millions of dollars a day. Our industry needs competent analysts to help solve these problems. Design Debug is a 3-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the design and/or manufacturing problem responsible for the failure. This course is designed for every manager, engineer, and technician working in the semiconductor field, designing complex integrated circuits, or supplying tools to the industry.

Participants learn to develop the skills to determine what tools and techniques should be applied, and when they should be applied. This skill-building series is divided into three segments:

1. Preparation for Design Debug: Participants learn the various steps required to prepare a sample for design debug. This includes physically preparing the sample, and generating the appropriate layout files, schematic files, and test vectors to ensure a successful activity.
2. The Debug Process: Participants learn the strengths and weaknesses of a variety of tools used for design debug, including electrical testing techniques, time-resolved emission, and other laser-based techniques such as Soft Defect Localization (SDL) and Light Assisted Device Alteration (LADA).
3. Case Histories and Laboratory Experiments: Participants identify how to use their knowledge through the case histories. They learn to identify key pieces of information that allow them to determine the possible cause of failure and how to proceed. Depending on the course setting, the instructor also has the participants work through several examples to localize and characterize partially functional and non-functional ICs.

Course Objectives

1. The seminar will provide participants with an in-depth understanding of the tools, techniques and processes used in design debug.
2. Participants will be able to determine how to set up a design debug analysis, ensuring that the analysis is done with the greatest probability of success.
3. The seminar will identify the advantages and disadvantages of the tools and techniques that are used for design debug.
4. The seminar offers several case histories, as well as interactive demonstrations of analysis techniques, so the analyst can get an understanding of the types of results they might expect to see with their equipment.
5. Participants will be able to set up basic test patterns for debug on integrated circuits.
6. Participants will be able to set up the basic layout, netlist, and schematic databases that are necessary for design debug.
7. Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

Instructional Strategy

By using a combination of instruction by lecture, exercises, and question/answer sessions, participants will learn practical approaches to the design debug process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.

Course Outline

1. Introduction and Overview
2. The Debug Process
1. Localizing the problem with test
2. Converting the production test pattern into a pattern for use in design debug
3. Using Shmoo
1. Voltage Levels
2. Temperature
3. Frequency
4. Physical Probing – Tools and Theory
1. Electron Beam Probing
2. Time-Resolved Emission
3. Optical Beam Probing
1. Resistive Interconnect Localization (RIL)
2. Soft Defect Localization (SDL)
3. Light Assisted Device Alteration (LADA)
4. Thermally-Induced Voltage Alteration (TIVA)
4. Laser Voltage Probing
5. EDA and How to Use It
1. Conversion of Design Databases
2. Automatic Test Pattern Generation Tools
1. FastScan
2. TetraMax
3. Encounter Test
3. Scan-Based Techniques
6. Preparing for Optical Probing
1. Package Decap
2. Die Thinning
3. Resolution Enhancement tips (solid immersion lenses)
4. Device Cooling
5. Cabling issues and signal integrity
7. Exercises
1. Classroom
2. Laboratory

Course Overview

Detailed Course Outline

Gary Woods

Gary Woods has been involved in the semiconductor and optics fields for 18 years. He graduated from Rice University in 1988 with a B.S.E.E. and B.A. (physics). After graduating from Rice University, he spent two summers at Texas Instruments developing advanced electron-beam voltage-probing instruments. He then attended Stanford University and obtained his Ph.D. in Applied Physics in 1997. His Ph.D. research centered on mid-IR nonlinear optical interactions in semiconductor quantum wells. From 1996-1998 he worked on quantum-well and nonlinear-optical physics as a postdoctoral researcher in the ECE department at the University of California, Santa Barbara. He joined Intel Corp. in 1998, where he worked on development of high-bandwidth optical probing techniques, including the Laser Voltage Probe, Time-Resolved Emission, and Dynamic Laser Stimulation. From 2000-2002 he was the CTO of a venture-funded startup company, which he co-founded, manufacturing fiber-optical equipment. From 2003-2006 he was a Senior Scientist at Credence Systems Corp.’s Diagnostics and Characterization group. His contributions included developing advanced measurement techniques using time-resolved emission and developing new laser-based probing technologies. He also provided applications support for several Credence customers’ debug efforts. He is now with Sooner Silicon Consulting Services. He holds 8 U.S. patents and has authored or co-authored more than 30 peer-reviewed publications, including more than 20 publications in the field of optical probing of silicon circuits.

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Last modified: 01/24/08