ESD and Latchup Design and Technology Short Course

Instructor: Dr. Steven H. Voldman

Course Overview

Electrostatic discharge is a 4 Billion (USD) a year problem for the Semiconductor Industry. This problem is likely to grow in the future as smaller devices are susceptible to damage at lower static voltages and latchup under more subtle conditions. Today, circuit designers and process integration engineers require a fundamental knowledge of device physics and electrothermal behavior of I/O structures in order to develop a process that is robust and can withstand the challenges of today’s varied environments in which ICs are fielded. Layout, ESD pulse behavior, semiconductor physics, and device modeling are all required to produce a successful product. Your industry needs competent engineers and scientists to help achieve these goals. ESD Design and Technology is a 2 to 4 day course that offers detailed instruction on a variety of subjects pertaining to ESD design and technology. This course is designed for every manager, engineer, and technician concerned with ESD at the I/O design level, the chip level, or supplying ESD tools and simulators to the industry.

Participants learn to develop the skills to determine what constitutes a good ESD design, how to recognize devices that can reduce ESD susceptibility, and how to design new ESD structures for a variety of technologies.

1. Overview of the ESD Failure Mechanism: Participants learn the fundamentals of ESD, the physics behind overstress conditions, test equipment, test protocols, and the results of failure.
2. ESD Technology Issues: Participants learn the behavior of different IC technologies under various ESD stress conditions. This includes CMOS, bipolar, BiCMOS, SOI GaAs, SiGe, SiGe:C and other strained silicon technologies. Participants also study the response of an IC’s substrates, wells, junctions, dielectric layers, and metallization to ESD.
3. ESD Circuit Design Issues: Participants learn how designers develop circuits to protect against ESD damage. This includes MOSFETs, diodes, off-chip driver circuits, receiver circuits, and power clamps.
4. Test Strategies: Participants learn the basics on how to test test structures, design screening tests, and how to perform burn-in testing effectively.

Course Objectives

1. The seminar will provide participants with an in-depth understanding of the ESD failure mechanism, test structures, equipment, and testing methods used to achieve robust ESD resistance in today’s components.
2. Participants will be able to gather ESD data, determine how best to plot the data, and make inferences from that data.
3. The seminar will identify the major issues associated with ESD, explain how they occur, how they are modeled, and how they are mitigated.
4. The seminar can be offered with several textbooks that cover the topic of ESD in much greater detail. The course author is a recognized expert in the field and has written the definitive textbook series on ESD.
5. Participants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.
6. Participants will be able to knowledgeably design ESD structures that are appropriate to assure the robustness of a component.
7. Participants will be able to identify appropriate tools to purchase when starting or expanding ESD test capabilities.

Instructional Strategy

By using a combination of instruction by lecture, written text material, problem solving and question/answer sessions, participants will learn practical approaches to the failure analysis process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field. The textbooks offer hundreds of pages of additional reference material the participants can use back at their daily activities.

Course Outline

1. Electrostatic Discharge Device Physics
1. ESD Models
2. ESD Testing and Qualification
3. ESD Failure Criteria
4. Electrothermal Physics
5. Electrostatic Discharge Failure Models
6. Semiconductor Devices and ESD Models
7. Latchup
2. Semiconductor Process and ESD Protection
1. Substrates and ESD
2. Well Design and ESD
3. Junctions, Salicide and ESD
4. Dielectrics and ESD
5. Aluminum, and Copper Interconnects and ESD
3. ESD in Advanced Technology
1. Silicon on Insulator and ESD
2. Silicon Germanium and ESD
3. Silicon Germanium Carbon and ESD
4. Strained Silicon Devices and ESD
5. Future Devices: FinFETS, MuGFETs, Nanotubes and the Future
4. ESD Fundamentals
1. ESD History
2. ESD Patents and Publications
3. Fundamentals of ESD Design
4. What makes ESD Design Unique?
5. ESD Design Methods
5. ESD MOSFET Design
1. Single Finger
2. Multi-finger
3. MOSFET Voltage Distribution Effects
4. MOSFET Wiring
5. MOSFET Contacts
6. MOSFET Ballasting
7. MOSFET Segmentation
8. MOSFET Ballasting
9. MOSFET Gate and Body Coupling
6. ESD Diode Design
1. Diode Anode Design
2. Diode Cathode Design
3. Diode Wiring Patterns
4. Diode Contacts
5. Diode String ESD Designs
6. Triple Well Diode Design
7. BiCMOS Diode Design
8. BiCMOS Triple Well Diode Design
7. ESD Circuits and Design
1. Chip Architecture and Synthesis
2. Input Node HBM Circuits
3. Input Node CDM Circuits
4. ESD Power Rail Circuits
5. ESD CMOS-Based ESD Networks
6. ESD BiCMOS-Based ESD Networks
8. ESD and Off-Chip Drivers
1. TTL, HSTL, GTL and SSTL
2. Single FET OCD
3. Mixed Voltage Interface OCD
4. Floating Well Circuitry
5. ESD Protection Tradeoffs
9. ESD and Receiver Networks
1. CMOS Receivers
2. CMOS Half Pass Transmission Gates
3. CMOS Full Pass Transmission Gates
4. CMOS Keeper Network
5. CMOS Pseudo-Zero VT Receivers
6. CMOS Zero VT Receivers
7. BiCMOS Receivers
8. BiCMOS Off-Chip Drivers
9. BiCMOS Differential Circuits
10. RF Circuits
10. ESD Power Clamps
1. Diode ESD Power Clamps
2. RC Triggered MOSFET Power Clamps
3. Voltage Triggered MOSFET Power Clamps
4. Bipolar ESD Power Clamps
5. Zener Triggered ESD Power Clamps
6. BVCEO Triggered SiGe ESD Power Clamps
7. Capacitively-Coupled GaAs Power Clamps
11. ESD Design Tools
1. Electrothermal Circuit Design
2. Electrothermal Device Design
3. ESD CAD Design

Course Outline

Dr. Steven H. Voldman

Dr. Steven H. Voldman is an IEEE Fellow for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He was the recipient of the ESD Association Outstanding Contribution Award in 2007.

He received his B.S. in Eng. Science from Univ. of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Eng. Physics (1986) and a Ph.D EE (1991) from Univ. of Vermont under IBM's Resident Study Fellow program.

Dr. Voldman was a member of the semiconductor development of IBM for 25 years. He was a member of the IBM’s Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS and Silicon Germanium, RF CMOS, RF SOI, smart power technology development and image processing technology teams.

In 2007, Dr. Voldman joined the Qimonda Corporation as a member of the DRAM development team, and reporting to Qimonda Europe working on 70, 58, 48 and 32 nm CMOS DRAM technology. Dr. Voldman was responsible for ESD technology strategy, ESD and latchup design manuals, and ESD design working on ESD protection in 512 Mb, 1 Gigabit, and 2 Gigabit DRAM products for HBM, MM, SDM, and CDM protection.

Dr. Voldman was chairman of the SEMATECH ESD Working Group, to establish a national strategy for ESD in the United States; this group initiated ESD technology benchmarking strategy, test structures and commercial test system strategy. He is a member of the ESD Association Board of Directors, ESDA Education Committee, as well ESD Standards Chairman for Transmission Line Pulse testing. Dr. Voldman was also the first chairman of the ESDA ESD Technology Roadmap committee and co-established the ESD Technology Roadmap in 2005. In 2005, he was the Subcommittee Chairman for both the Latchup Sub-committee for the International Reliability Physics (IRPS) and the EOS/ESD Symposium, the ESD Chairman for the International Physical and Failure Analysis (IPFA) Symposium, and presently serving on the technical program committees for the Taiwan ESD Symposium, International Conference on Electromagnetic Compatibility (ICEMAC, Taipei, Taiwan), Bipolar Circuit Technology Meeting (BCTM), IRPS, and EOS/ESD Symposium; Steve has provided tutorials on ESD, latchup, failure mechanisms, and RF ESD devices to the IRPS, EOS/ESD, BCTM, and IPFA.

Dr. Voldman also has written an article for Scientific American in October 2002. Dr. Voldman is an author of the book ESD: Physics and Devices, the second book ESD:Circuits and Devices, a third book, ESD: Radio Frequency (RF) Technology and Circuits, and fourth text, Latchup, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design.

In the ESD Association, Voldman initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 28 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, and China. He also provides tutorials internationally on ESD protection.

Dr. Voldman has written over 150 technical papers between 1982 and 2007. He is a recipient of over 169 issued US patents and 98 US patents pending, in the area of ESD and CMOS latchup. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents; and has also founded a limited liability corporation (LLC) consulting business supporting ESD design, teaching, patents and patent litigation.

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In the U.S. and Europe, Dr. Voldman’s books, ESD: Physics and Devices and ESD: Circuits and Devices, are included in the price.

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Registration Form for Public Courses (Printable Version)

Please note that registration within 14 days of the course is subject to $100 surcharge.

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Last modified: 01/24/08