IC Packaging Technology and Challenges Course

Instructor: Dr. Gay Samuelson

Course Overview

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The industry is also pushing to use semiconductor devices in an increasing array of applications. To accomplish this, the industry is also driving prices down. This has created a number of challenges related to the packaging of these components. Semiconductor Packaging Technology is a 2 to 3 day course that offers detailed instruction on the technology issues associated with today’s semiconductor packages. We place special emphasis on current package technology issues like lead-free solders, low-k dielectrics, and tools for package analysis. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.

By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.

Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:

1. Packaging Technology Overview: Participants study the Packaging portion of the International Technology Roadmap for Semiconductors (ITRS) to learn about the issues facing packaging technology. They learn why use conditions have become critical to semiconductor packaging for today’s designs.
2. Current Issues: Participants learn the issues surrounding the introduction of low-k materials on the die and their impact on packaging, the introduction of lead-free solders and their impact on packaging, and the impact of packaging when deciding between “system on a chip” and “system in a package” configurations.
3. Thermal Simulations: Participants learn the fundamentals of reliability for packaging. They also study the tools and techniques used for analyzing problems with packaging.
4. Future Semiconductor Packages: Participants discuss the future of semiconductor packaging. This includes technologies that are currently being introduced, like Microelectromechanical Systems (MEMS), nano-scale devices, and devices that will be used in the approaching convergence of electronics and biology.

Course Objectives

1. The seminar will provide participants with an in-depth understanding of semiconductor packaging technology and its technical issues.
2. Participants will understand the issues behind packaging technology and why we are facing certain predicaments.
3. The seminar will identify the key issues related to the continued growth of the semiconductor industry. This includes the need for materials that can withstand high power dissipation, and materials that can mitigate the increasing fragility of the die because of low-k dielectrics.
4. Participants will understand how package reliability, power consumption and device performance are interrelated.
5. Participants will be able to make decisions about how to construct and evaluate new packaging designs and technologies.
6. The participant will also be introduced to polymers, solders, and a host of materials being considered for advanced packaging.

Instructional Strategy

By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.

Course Outline

1. Packaging Trends
1. Global Business Trends
2. Technology Trends and Implications for Packaging
3. International Technology Roadmap for Semiconductors: What it is and What it Says About Packaging
2. Use Conditions
1. Meaning of Use Conditions
2. How is the Methodology Applied and What is the Benefit
3. Lead Free: the Politics, the Key Technical and Logistic Challenges
4. Integration Dilemma: Why System on a Chip (SOC) vs. System in a Package (SIP)
5. Reliability and Failure Mechanisms of Plastic Packages
6. Industry Consortia for Semiconductor Packaging
1. Assembly Analytical Forum (AAF)
2. Advanced Materials Failure Analysis Workshop (AMFA)
7. Polymers
1. Chemistry, Properties, Measurement, Use in Packaging
2. Liquid Crystal (LC) and Polyimide (PI) Polymers
8. Case Studies on Failure Mechanisms
1. Connectors
2. Sealants
3. Thermal Interface Materials (TIMs) and Shock Absorbers
9. Manufacturing with Lead Free Solders
1. Implications for Bumping, Under-Bump Metallization (UBM), Solder Joint Cracks and ILD Damage
2. Metallurgical Implications of Reflow Using Lead Free Solders
3. Electromigration Comparisons of Al, Cu and Solders
4. Tin Whiskers in Lead Free Applications
5. Mechanism of Whisker Formation
10. Wrap-Up

Course Overview

Dr. Gay Samuelson

Dr. Samuelson recently retired as an engineering project manager from Intel's Assembly Technology development Q&R organization. She has also managed a Quality and Reliability analytical laboratory, pacemaker hybrid assembly production, and other products at MicroRel. Additionally she developed photovoltaic modules and liquid crystal displays for Motorola. She holds an M.S. and Ph.D. in molecular biology from the University of Wisconsin.

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For information on dates in Southeast Asia, email KS Chuah at ks.chuah@semitracks.com

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Last modified: 01/24/08