IC Packaging Technology

Integrated Circuit packaging has always been integral to IC performance and functionality. An IC package serves many purposes: (1) pitch conversion between the fine features of the IC die and the system level interconnection, (2) chemical, environmental and mechanical protection, (3) heat transfer, (4) power, ground and signal distribution between the die and system, (5) handling robustness, and (6) die identification among many others. Numerous critical technologies have been developed to serve these functions, technologies that continue to advance with each new requirement for cost reduction, space savings, higher speed electrical performance, finer pitch, die surface fragility, new reliability requirements, and new applications. Packaging engineers must fully understand these technologies to design and fabricate future high-performance packages with high yields at exceptional low-costs to give their company a critical competitive advantage.

This two-day class will detail the vital technologies required to construct IC packages in a reliable, cost effective, and quick time to market fashion. When completed, the participant will understand the wide array of technologies available, how technologies interact, what choices must be made for a high-performance product vs. a consumer device, and how such choices impact the manufacturability, functionality, and reliability of the finished product. An emphasis will be given to manufacturing, processes and materials selection tailoring and development. Each fundamental package family will be discussed, including flip chip area array technologies, Wafer Level Packaging (WLP), Fan-Out Wafer Level Packaging (FO-WLP), and the latest Through Silicon Via (TSV) developments. Additionally, future directions for each package technology will be highlighted, along with challenges that must be surmounted to succeed.

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Course Dates | Location

September 27-28, 2017 | Dallas, TX, USA
(Price available until Wed. Sept. 6)

Cost

$1,295
$1,195

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Please fax the printable registration form for public courses to us at 1-866-205-0713 to complete your order.

Additional Information

For dates and locations in South East Asia, please contact us at se-asia.courses@semitracks.com.

Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

  1. Molded Package Technologies. Participants learn the fundamentals of molding critical to leaded, leadless, and area array packaging, enabling them to eliminate problems such as flash, incomplete fill, and wire sweep.
  2. Flip Chip Technologies. Participants learn the fundamentals of plating, bumping, reflow, underfill, and substrate technologies that are required for both high performance and portable products.
  3. Wafer Level Packages. Participants learn the newest technologies that enable the increasingly popular Wafer Chip Scale Level Packages (WCSPs) and Fan-Out Wafer Level Packages (FO-WLPs).
  4. Through Silicon Via Packages and Future Directions. Participants will know the latest advances in the recently productized TSV technology, as well as future directions that will lead to the products of tomorrow.

Course Objectives

  1. The course will supply participants with an in-depth understanding of package technologies current and future.
  2. Potential defects associated with each package technology will be highlighted to enable the student to identify and eliminate such issues in product from both internal assembly and OSAT houses.
  3. Cu and solder plating technologies will be described with special emphasis on package applications in TSVs and Cu pillars for FO-WLPs. Emphasis will be placed on eliminating issues such as reliability, non-uniformity, void free thermal aging performance, and contamination free interfaces.
  4. New package processes employed in Through Silicon Via production will be described, along with current cost reduction thrusts, to enable the student to understand the advantages and limits of the technologies.
  5. Temporary bonding and wafer thinning processes will be highlighted, as well as the cost reduction approaches currently being pursued to enable wider adoption of TSV packages.
  6. The trade-offs between silicon, glass, and organic interposers will be highlighted, along with the processes used for each.
  7. Participants will gain an understanding of the surface mount technologies that enable today’s fine pitch products.
  8. The class will provide detailed references for participants to study and further deepen their understanding.

Course Outline

Day 1

  1. The Package Development Process as a Package Technology
    1. Materials and Process Co-Design
  2. Molded Package Technologies
    1. Die Attach
      1. Plasma Cleans
    2. Wire Bonding
      1. Au vs. Cu vs. Ag
      2. Die Design for Wire Bonding
    3. Lead Frames
    4. Transfer and Liquid Molding
      1. Flash
      2. Incomplete Fill
      3. Wire Sweep
      4. Green Materials
    5. Pre- vs. Post-Mold Plating
    6. Trim Form
    7. Saw Singulation
    8. High Temperature and High Voltage Materials

Day 2

  1. Flip Chip and Ball Grid Array Technologies
    1. Wafer Bumping Processing
      1. Cu and Solder Plating
      2. Cu Pillar Processing
    2. Die Design for Wafer Bumping
    3. Flip Chip Joining
    4. Underfills
    5. Substrate Technologies
      1. Surface Finish Trade-Offs
      2. Core, Build-up, and Coreless
    6. Thermal Interface Materials (TIMs) and Lids
    7. Fine Pitch Warpage Reduction
    8. Stacked Die and Stacked Packages
    9. Material Selection for Board Level Temperature Cycling and Drop Reliability
  2. Wafer Chip Scale Packages
    1. Redistribution Layer Processing
    2. Packing and Handling
    3. Underfill vs. No-Underfill
  3. Fan-Out Wafer Level Packages
    1. Chip First vs. Chip Last Technologies
    2. Redistribution Layer Processing
    3. Through Mold Vias
  4. Through Silicon Via Technologies
    1. Current Examples
    2. Fundamental TSV Process Steps
      1. TSV Etching
      2. Cu Deep Via Plating
      3. Temporary Carrier Attach
      4. Wafer Thinning
    3. Die Stacking and Reflow
    4. Underfills
    5. Interposer Technologies: Silicon, Glass, Organic
  5. Surface Mount Technologies
    1. PCB Types
    2. Solder Pastes
    3. Solder Stencils
    4. Solder Reflow

Instructor Profile

Mr. Darvin Edwards, B.S. Physics

Darvin Edwards

Darvin R. Edwards received the B.S. degree in Physics from Arizona State University, Tempe, AZ, in 1980 and joined Texas Instruments soon after. Initially at TI, he developed integrated test structures such as strain gauges, moisture sensors, thermal sensors, and structures to determine the impact of package stresses on IC thin film layers. He developed a set of IC design rules for packaging that has been continuously updated and is still in use today. He then worked to build TI’s competence in thermal characterization and thermal management. He wrote a thermal characterization modeling program that was used within TI from 1993 through 2004 and built TI's thermal labs. With JEDEC, he wrote the thermal test board standards.

Elected TI Fellow in 1999, he was manager of the Advanced Package Modeling and Characterization group from 1997 through 2012. His modeling team was responsible for thermal, electrical, and stress analysis for a wide range of product families, as well as ensuring reliability, successful qualification and introduction of products to the market. Packages and technologies he has helped develop include TSV, POP, Cu Pillar, Stacked Die, MCM, FC-BGA, PBGA, QFN, CSP, WLCSP, QFP, LOC, multi-die QFP, and SOICs.

In 2013, Darvin took responsibility for Analog Chip/Package Codesign, developing innovative test structures and reliability design guidelines for TI’s new analog process nodes, including those of high voltage components. Additionally, he created and codified a risk assessment process that was implemented worldwide for TI’s new package development projects. During his career at TI, Darvin also managed at various times advanced package FA technique development, adhesion characterization development, and Sun Flip-Chip microprocessor package development.

After retiring from TI in late 2013, Darvin formed Edwards’ Enterprise Consulting LLC which focuses on bringing expert insights to IC package reliability, failure analysis, and thermal management issues. He is an active professional development instructor for the Electronic Components and Technology Conference, has taught courses for both Pico Tech Resources and SemiTracks on topics such as Package Design, Package Reliability, Package Materials, and Surface Mount Technologies. He has regularly served as an expert witness in patent litigations and has spoken at many universities to encourage students to pursue careers in IC Packaging.

Darvin is a two-time past chair of the SRC GRC Interconnect and Packaging Sciences’ Science Area Coordinating Committee, and was TI’s IPS SAC and TAB representative for eight years. He served as a liaison on many SRC research projects, working regularly with various universities and research institutes to coordinate TI’s external packaging research interests.

Professional activities have included over 35 years of service on the Applied Reliability program selection committee of the ECTC, which he has chaired numerous times. Darvin also authored five JEDEC standards including the PCB specifications for low and high effective thermal conductivity test cards. He has contributed to both the ITRS and iNEMI roadmaps. He has authored and co-authored over 60 papers and articles in the field of IC packaging, including two best paper awards and an Intel best student paper award, has written two book chapters, and has given multiple keynote addresses, lectures, tutorials, and short courses. He holds 23 US patents. Darvin is an IEEE Senior Member and is serving his fourth term on the CPMT Board of Governors.