Semiconductor Reliability Short Course

Instructor: Christopher Henderson

Course Overview

Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. Analysis and experimentation is now performed at the wafer level instead of the packaging level. This requires knowledge of subjects such as: design of experiments, testing, technology, processing, materials science, chemistry, and customer expectations. While reliability levels are at an all-time high level in the industry, rapid changes may quickly cause reliability to deteriorate. Your company needs competent engineers and scientists to help solve these problems.

Semiconductor Reliability is a 3 day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability. This course is designed for every manager, engineer, and technician concerned with reliability in the semiconductor field, using semiconductor components, or supplying tools to the industry.

Participants learn to develop the skills to determine what failure mechanisms might occur, and how to test for them, develop models for them, and eliminate them from the product.

1. Overview of Reliability and Statistics: Participants learn the fundamentals of statistics, sample sizes, distributions and their parameters.
2. Failure Mechanisms: Participants learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die level and at the package level. These include: time-dependent dielectric breakdown, hot carrier degradation, electromigration, stress-induced voiding, moisture, corrosion, contamination, thermomechanical effects, etc.
3. Test Structures: Participants learn how test structures can be designed to help test for a particular failure mechanism.
4. Test Strategies: Participants learn the basics on how to test test structures, design screening tests, and how to perform burn-in testing effectively.

Course Objectives

1. The seminar will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment, and testing methods used to achieve today’s high reliability components.
2. Participants will be able to gather data, determine how best to plot the data and make inferences from that data.
3. The seminar will identify the major failure mechanisms, explain how they are observed, how they are modeled, and how they are eliminated.
4. The seminar offers a variety of video demonstrations of analysis techniques, so the participants can get an understanding of the types of results they might expect to see with their equipment.
5. Participants will be able to identify basic test structures and how they are used to help quantify reliability on semiconductor devices.
6. Participants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.
7. Participants will be able to identify appropriate tools to purchase when starting or expanding a laboratory.

Instructional Strategy

By using a combination of instruction by lecture, video, problem solving and question/answer sessions, participants will learn practical approaches to the failure analysis process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field. The handbook offers hundreds of pages of additional reference material the participants can use back at their daily activities.

The Semitracks Analysis Instructional Videos

One unique feature of this workshop is the video segments used to help train the students. Reliability Analysis is a visual discipline. The ability to identify nuances and subtleties in graphical data is critical to locating and understanding the defect. Some tools output video images that must be interpreted by engineers and scientists. No other course of this type uses this medium to help train the participants. These videos allow the analysts to directly compare material they learn in this course with real analysis work they do in their daily activities.

Course Outline

1. Introduction to Reliability
1. Basic Concepts
2. Definitions
3. Historical Information
2. Statistics and Distributions
1. Basic Statistics
2. Normal Distribution
3. Lognormal Distribution
4. Weibull Distribution
5. Exponential Distribution
6. Which Distribution Should I Use?
7. Data Handling
3. Die-Level Failure Mechanisms
1. Time Dependent Dielectric Breakdown
2. Hot Carrier Damage
3. Negative Bias Temperature Instability
4. Electromigration
5. Stress Induced Voiding
4. Package Level Mechanisms
1. Ionic Contamination
2. Moisture/Corrosion
3. Thermo-Mechanical Stress
4. Thermal Stress/Cycling
5. Use Condition Mechanisms
1. Electrical Overstress/ESD
2. Radiation
6. Test Structures and Test Equipment
1. Test Structures
1. Parametric Test Structures
2. Reliability Test Structures
3. Self-Stressing Test Structures
2. Test Equipment
1. Packaged Part Testing
2. Wafer Level Testing
7. Developing Screens, Stress Tests, and Life Tests
1. Burn-In
2. Life Testing
3. HAST
8. Package Attach (Solder) Reliability
9. Board Level Reliability Mechanisms
10. Calculating Chip and System Level Reliability
11. Future Reliability Challenges

Course Overview

Course Outline

Christopher Henderson, President of Semitracks

Christopher Henderson received his B.S. in Physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Chris is the President and one of the founders of Semitracks Inc., a United States based company that provides education and training to the semiconductor industry. Chris also teaches courses in failure analysis, reliability and semiconductor technology for the semiconductor industry. From 1988 to 2004 he worked at Sandia National Laboratories, where he was a Principal Member of Technical Staff in the Failure Analysis Department and Microsystems Partnerships Department. His job responsibilities have included failure and yield analysis of components fabricated at Sandia’s Microelectronics Development Laboratory, research into the electrical behavior of defects, and consulting on microelectronics issues for the DoD. He has published over 20 papers at various conferences in semiconductor processing, reliability, failure analysis, and test. He has received two R&D 100 awards and two best paper awards. Prior to working at Sandia, Chris worked for Honeywell, BF Goodrich Aerospace, and Intel. Chris is a member of IEEE and EDFAS (the Electron Device Failure Analysis Society).

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For information on dates in Southeast Asia, email KS Chuah at ks.chuah@semitracks.com

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Last modified: 01/24/08