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May 8, 2011


Ask the ExpertsAsk the Experts

Q: Is there a standard for SEU testing?

A: Yes there is. JEDEC issued JESD-89 in 2007 to cover SEU testing. There are several parts to the document; be sure to read each one so you know how to apply the testing to your situation.

To post, read, or answer a question, visit our forums. We look forward to hearing from you!

May 1, 2011


Electronic Gun Configurations for Scanning Electronic Microscopes
By Christopher Henderson

The Scanning Electron Microscope is a basic instrument for analysis and characterization. We will cover the basic configuration of the electron guns in this article. Scanning Electron Microscopes (SEMs) fall into three basic configurations, Tungsten, Lanthanum Hexaboride or LaB6 and field emission. Within the field emission category, there are two basic configurations: the cold cathode configuration and the Schottky Emitter configuration.

Figure 1 shows the basics of a tungsten-based system. In a standard tungsten system, a bias is placed across the filament; the current through the filament heats it. At high temperatures, the material emits electrons, which can then be accelerated down the column. The high voltage power supply between the Wehnelt cylinder, filament, and anode plate determines the primary electron beam energy.

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Figure 2 shows the basics of a lanthanum hexaboride system. Lanthanum hexaboride, also known as LaB6, emits a higher number of electrons than a tungsten filament, permitting higher quality images. In this gun configuration, a heating coil encompasses the LaB6 rod to heat it. As with the tungsten system, the high voltage power supply lies between the Wehnelt cylinder and anode plate to determine the primary electron beam energy.

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Another method for generating electrons is the field emission gun. A schematic of a field emission tip is shown in Figure 3. When the cathode forms a very sharp tip (typically 100 nm or less) and the cathode is placed at a negative potential with respect to the first anode so that the local field at the tip is very strong (greater than 10 to the 7 Volts per centimeter), electrons can tunnel through the potential barrier and become free. Although the total current is lower than either the tungsten or the LaB6 emitters, the current density is between 10 to the 3 and 10 to the 6 Amps per centimeter. Thus, the field emission gun is hundreds of times brighter than a thermionic emission source. Furthermore, since the electrons are field generated rather than thermally generated, the tip remains at room temperature. Tips are usually made from tungsten etched in the <111> plane to generate the lowest work function. Because a native oxide will quickly form on the tip even at moderate vacuum levels (10 μPa), a high vacuum system (10 nPa) is needed. To keep the tip diameter sufficiently small, the cathode warmed to 800-1000 °C or rapidly heated to approximately 2000 °C for a few seconds to blow off material.

This table below summarizes the basic capabilities of the four basic configurations, where we break the cold field emission and Schottky field emission systems into their own separate groups.The highest performers are the field emission systems, which include cold cathode and Schottky. The high brightness and sharp tip leads to high resolution and longer source lifetimes. Notice that both tungsten and LaB6 have lower brightness, lower resolution, and reduced source lifetimes. However, the lower vacuum requirements can facilitate more rapid sample exchange, especially when venting the column is necessary. For more information on the Cold Cathode and Schottky field emission systems, please see the Technical Tidbit on this topic elsewhere in this newsletter.Higher tunnel magneto resistance improved the read speeds to on the order of 10 nsec. Unfortunately, the current needed for MRAM devices increases as the dimensions decrease, limiting the usefulness of this type of device.

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April 22, 2011


Course Spotlight

Online Training - Photovoltaics Material

If you are interested in the area of Photovoltaics, but aren’t able to attend the upcoming courses; we encourage you to explore the option of our Online Training system.

Our online semiconductor training courses can be customized for your job function. The structure of the material allows you, the user, to learn when you have a few moments free, alleviating the need to carve a large block out of your schedule. Other disciplines allow you to cross-train for potential promotions or transfers or to simply do a better job in your current position. The material is always current and interactive, allowing you to learn the material easily. You can search our databases for answers to questions you might have or simply use it as a reference.

If you aren’t quite ready to sign up for an account, please contact us at This email address is being protected from spambots. You need JavaScript enabled to view it. and we will create a temporary two-week account for you to try out our system.

April 15, 2011


Thin Film Photovoltaics Technology Spotlight

There are actually two major technology groups working on solar energy: silicon crystalline technology, and thin film technology. Since the 1980s, stunning breakthroughs in thin- film photovoltaic technology have made clean, light- generated electricity more feasible and economical. Many people believe that thin-film technologies might ultimately be the most cost-effective method to bring solar energy to the world on a large scale. As many companies rapidly introduce new technologies to harness solar power, tracking developments--let alone understanding them--can be daunting. Semitracks' one-day Thin Film Photovoltaics Technology course analyzes and distills the most important aspects of this complex technology. Learn more at:

http://www.semitracks.com/index.php/en/courses/public-courses/photovoltaics/thin-film-photovoltaics-technology

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April 8, 2011


Ask the ExpertsAsk the Experts

Q: What is the difference between MTBF (Mean Time Between Failures) and MTTF (Mean Time To Failure)?

A: At first glance, the two terms seem to be the same, but there is a fundamental difference in how they are applied. MTTF assumes that the system is not repaired, so MTTF is basically the integral from 0 to infinity of the fraction of all failures for a given time with respect to time (add the equation). MTBF assumes the system can be repaired, and is repaired instantaneously. The equation for MTBF adds the time variable explicitly into the integral. Therefore, MTTF is a more appropriate variable for a system or component that cannot be repaired, like an IC, whereas MTBF is more appropriate or systems that can be repaired, like an automobile, or PCB.

To post, read, or answer a question, visit our forums. We look forward to hearing from you!

April 1, 2011


Future Memory Technologies – Part 4
By Christopher Henderson

This month we conclude our series of articles on the future of memory. The final future memory technology we will cover is based on spintronics or spin transport electronics. Another common term for this technology is magnetoelectronics. These devices are also sometimes referred to as MRAM, or Magnetoresistive Random Access Memory. MRAM has been in development since the 1990s, and several companies have introduced production devices. The basic memory cell is a dual stripe of anisotropic magnetoresistive (AMR) layers separated by a nonmagnetic spacer. AMR materials were also used in the read head of magnetic recording hard disk drives. AMR is a change in the resistance of ferromagnetic conductors depending on the angle between the magnetization and the current. The magnitude of this effect is only about 2% for the most common magneto-striction-free NiFe or NiFeCo alloys suitable for device applications. The simplest form of GMR or Giant Magnetoresistive films consist of two magnetic layers separated by a Cu spacer, and had a magnetoresistance ratio of 6% initially and later more than 10% with improvements. The image below shows a drawing of a typical MRAM cell.

Figure 1. Drawing depicting a Magnetoresistive RAM cell or MRAM cell

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Higher tunnel magneto resistance improved the read speeds to on the order of 10 nsec. Unfortunately, the current needed for MRAM devices increases as the dimensions decrease, limiting the usefulness of this type of device.

Researchers working to address problems with MRAM technology discovered that it is possible to use an alternate quantum mechanical property in the magnetic tunnel junction by changing the magnetic orientation of the thin magnetic layer. Basically, charge carriers such as electrons have a quantum unit of angular momentum or spin. An electrical current is generally unpolarized, consisting of 50% spin-up and 50% spin-down electrons whereas a spin-polarized current contains more electrons with a particular spin state. Researchers have demonstrated that it is possible to transfer spin angular momentum to a small magnetic element through a spin-polarized current. Spin-transfer torque RAM or STT-RAM has the advantages of lower power consumption and better scalability compared to conventional MRAM. In particular, the write current scales down with size, whereas MRAM write current scales up as the size of the cell decreases. Today, Sony and Hitachi are working as a team to develop this technology and introduce commercial parts in the near future.

Figure 2. Cross-section of a Spin Transfer Torque (STT) RAM cell.

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The graph below shows the scaling of current for both MRAM and Spin Transfer Torque RAM. Notice that the current scales down as the feature sizes decrease for STT-RAM. The opposite is true with regular MRAM.

Figure 3. Current vs. cell width for MRAM and STT-RAM devices.

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In conclusion, there are a number of potential memory technologies that may take the place of flash memory in the future. This table shows several of the leading candidates: ferroelectric memory, magnetoresistive RAM, phase-change RAM, and spin transfer torque RAM. Each device has its advantages and disadvantages. Current generation flash memory is increasingly limited by its cycle endurance. High voltage is required to write and erase flash memory, and the write power is very high. Ferroelectric memory solves the “high voltage” and “write power” issue, but falls short on endurance. MRAM has a high endurance level, but the write power becomes worse as the devices scale down. Phase-change memory has low write power, but is somewhat limited in endurance. STT-RAM shows the most promise, but its development is still in its infancy, and the problems with write current have not been completely solved. Magnetic nanopillars is in its infancy, and is not shown on this table. Researchers and device manufacturers are likely to pursue these technologies for some time to determine which one will ultimately replace Flash as the reigning non-volatile memory.

Table 1. Comparison of Memory Technologies.

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March 8, 2011

Ask the ExpertsAsk the Experts

Q: What types of techniques can be used to highlight bond pad cratering?

A: One technique that can highlight bond pads for cratering using an optical microscope is nickel decoration. The aluminum bondpad is etched away, and the chip is placed in a nickel plating solution for several minutes. The nickel will first adhere to the cracks, providing contrast in the optical microscope.

To post, read, or answer a question, visit our forums. We look forward to hearing from you!

March 1, 2011


Future Memory Technologies – Part 3
By Christopher Henderson

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Figure 1. Basic concept behind magnetic nanopillar memory operation.

Researchers are also investigating other types of memories for the future. As we approach the limitations imposed by physics on charge- based memories, new architectures will be needed to scale down further. Onepotentialmemorytechnologythatisgeneratingsome interest is magnetic nanopillars. Another commonly used acronym for nanopillar technology is RAMA. It stands for reconfigurable array of magnetic automata. Researchers have already demonstrated that a random array of up and down polarized ferromagnetic pillars (CoFe2O4) embedded in a ferroelectric or multiferroic matrix (e.g., BiFeO3) can have their magnetizations rotated from being perpendicular to the pillar (and the film) surface to being in-the-plane of the film with the application of a modest electric field.

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Figure 2. Construction of magnetic nanopillar devices.

This technique is being explored to create magnetic nanopillar devices. Wires are formed on a substrate using nanoimprint lithography, electron beam lithography, or other lithographic techniques. The ferromagnetic pillars are constructed through lithographic methods or polymeric self-assembly.

The ferroelectric material resides in columns within the piezoelectric material or matrix to form potential connections between two conducting planes. The lower part of the ferromagnetic material forms the nanopillar, while the top portion is the colossal magnetocapacitive material, such as LaPrCaMnO3, LaSrMnO3 or other manganite. This material is called a colossal magnetocapacitive (CMC) material, because such a capacitor built of this compound can exhibit large changes in capacitance with changes in magnetic field. Patterning metal, etching the material where it is not needed, and depositing insulating material between the conductors form the top connections. Researchers at the University of Virginia and others have described this type of approach.

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Table 1. Comparison of Magnetic Nanopillar or RAMA with standard CMOS SRAM technology.

Notice that RAMA, or nanopillar technology has some potentially significant advantages over standard memory technology. Notice that the nanopillar technology can be made through polymeric self- assembly, potentially reducing the cost of the device. The cell size can be smaller, allowing for greater bit density. The switching energies are much lower than for standard memory, but the switching speeds are also much lower. RAMA can also be made to be compatible with existing CMOS processing.

February 22, 2011


Technical Tidbit
Dice Before Grinding

Usually, wafers are ground down before the sawing operation. However, some organizations have been exploring a process where the sawing operations occur first, followed by the backgrinding operation. This is sometimes referred to as “Dice Before Grinding”, or DBG. The conventional grind before sawing is shown in the upper row. Three variations of the DBG approach are shown in the lower rows. DBG can be done with or without Chemical Mechanical Polish, or CMP. CMP can be useful when a higher quality interface is needed between dice. DGB can also be accomplished using standard wafer saw processes, or with reactive ion etching.

One concern with thin dice is how to handle them. The dice are especially prone to damage during pick and place operations. The key is to initiate the peeling process from the backing tape without damaging the dice. This diagram shows an approach to doing just that. This process involves raising and then lowering the ejector assembly. By raising it, one can initiate the peeling process at the edge of the die. By then lowering the ejector assembly, one can achieve a controlled peeling process in which the backing tape peels away from the die, but the die is held in position by the ejector pins.

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February 15, 2011


Course Spotlight

Semitracks Online Training Spotlight

Our online semiconductor training courses can be customized for your job function. The structure of the material allows you, the user, to learn when you have a few moments free, alleviating the need to carve a large block out of your schedule. Other disciplines allow you to cross-train for potential promotions or transfers or to simply do a better job in your current position. The material is always current and interactive, allowing you to learn the material easily. You can search our databases for answers to questions you might have or simply use it as a reference.

Learn more at: http://www.semitracks.com/index.php/online-training

February 8, 2011


Ask the ExpertsAsk the Experts

Q: I am detecting sulfur on the top of packaged devices as well as on the bond pads of printed circuit boards in our manufacturing process. What might be causing this contamination?

A: There are several common sources of sulfur in PCB manufacturing and assembly. They include: outgassing of elastomers vulcanized with sulfur, contamination in the PCB board itself, sulfur in the solder resist material, stop-off lacquer, contamination from paper or paperboard (cardboard) materials, and industrial environments or city environments with high sulfur or sulfide concentrations.

February 1, 2011


Future Memory Technologies – Part 2
By Christopher Henderson

Another contender as a future non-volatile memory technology is Resistive Random Access Memory, sometimes shortened to RRAM or ReRAM. A prototype RRAM chip is shown in Figure 1. Several major manufacturers are working on RRAM, including: Samsung, Micron, Macronix, and Elpida Memories. The technology is somewhat similar to Conductive Bridging RAM and Phase Change Memory, which we discussed in the previous issue. IMEC in Belgium has also done extensive research into this technology.

Figure 1. 128 Kbit RRAM array from a collaboration between AIST, Sharp, ULVAC, and Kanazawa University.

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Figure 2. Cross-section of an RRAM cell. The switch is located in the backend of the process.

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The basic concept is that one can create a conducting path through a dielectric layer by applying a high voltage (see Figure 2). The conducting path, or filament can be reset, restoring the high resistance path and reformed to create a low resistance path at will. This filament path may actually be multiple paths, according to researchers. There are different types of materials that can exhibit this behavior. They include perovskites, chalcogenides, and transition metal oxides. Some of the leading transition metal oxides include nickel oxide, titanium oxide, tungsten oxide, hafnium oxide, and heterostructures such as aluminum oxide/titanium oxide. Ironically, even silicon dioxide can be used for this application. The failure mechanism engineers try to avoid in standard CMOS, time-dependent dielectric breakdown, is the mechanism by which the programming occurs.

Figure 3. Forming, reset and set currents for a Resistive RAM test structure (area = 2x10-5 cm2, HfO2 thickness of 5nm and TixNy electrodes. The researchers used a current compliance of 10-4 Amps

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RRAM has the potential to become the front runner for future memory technologies. RRAM can operate much faster than Phase Change Memory. The switching time can be on the order of 10ns. Compared to MRAM, RRAM has a much smaller cell size. The cell size is less than 8F2, where F is the smallest feature size. It can also function at lower operating voltages than standard flash memories. RRAM also has the potential to scale down below 30nm. While standard flash memory is now below 30nm, the cell size is larger, so RRAM can still accommodate more cells in the same silicon area. Researchers believe that the mechanism might involve oxygen motion, which might allow for scaling down to as low as 2nm. The filament dimensions during the forming process are also key factors to a stable, reliable device(1)

(1) G. Bersuker, et. al., “Diode-less Nano-scale ZrOx/HfOx RRAM Device with Excellent Switching Uniformity and Reliability for High-density Cross-point Memory Applications,” Proc. Int. Elec. Dev

January 15, 2011


Technical Tidbit – Backgrinding

Wafer backgrinding is a common technique to thin dice for packaging in thin profile applications. Understanding the behavior of silicon during backgrinding is important to achieve success. Generally speaking, silicon is a brittle material, breaking with sharp edges and cracks (similar to glass). However, Si-II (pronounced “silicon-two”) has lower yield strength, which is relatively easily deformed with better elongation. This is similar to most metals. For reference, Si-II is a work-hardened phase of silicon, where the stress-strain curve of the material changes somewhat from unworked crystalline silicon, or Si-I (pronounced “silicon-one”). So based on the morphology, a ductile grinding mechanism is dominant in poligrinding. It is preferred as well for rough grinding, it is a mixed mechanism of ductile and brittle grinding. This generates amorphous silicon, or a-Si upon interaction.

These two images show the results of brittle grinding and ductile grinding. Notice the chunks of material that have been ripped out due to brittle grinding. Ductile grinding tends to leave gouges in the material with extruded material immediately adjacent to the trench.

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Poligrinding and rough grinding show multi-layer damage structures, which is the result of ductile grinding. The images on the right show the damage that occurs with both techniques. Notice the amorphous silicon layer in gold, the plastically deformed layer in cyan, the elastically deformed layer in magenta, and the undisturbed crystalline silicon in gray. Due to difference in load pressures, each layer in rough grinding samples is thicker than its counterpart in poligrinding samples. In rough grinding samples, dimples and sub- surface cracks caused by brittle grinding are irregularly distributed.

To summarize the grinding process for wafer thinning, there are two identifiable mechanisms: ductile and brittle grinding. In poligrinding, the ductile mechanism is dominant and in rough grinding, both ductile and brittle grinding occur. Both grinding processes create damage that extends for some distance into the silicon. The rough grinding process produces a damage layer of amorphous silicon that is about 70 nanometers thick, a plastically deformed layer of about 3.5 microns, and a stressed region of about 20 microns. Poligrinding generates much less stress. The amorphous silicon layer is only a few nanometers thick, and the plastically deformed and stressed layers are each approximately 2 microns thick.

January 8, 2011


Ask the ExpertsAsk the Experts

Q: What is the difference between troubleshooting and failure analysis?

A: Troubleshooting and failure analysis have quite a bit of overlap in the semiconductor industry. Troubleshooting usually refers to the process of localizing the problem, whether that be on a chip, inside an electronic component, or within a system. Troubleshooting normally implies finding the problem, and potentially fixing or replacing the component with the problem. As such, we normally think of troubleshooting without regards to fixing the underlying cause. Failure analysis is usually a defined (quite often required) activity that involves not only troubleshooting, but investigation into the root cause of a problem as well as development of a corrective action. Therefore, in failure analysis, we work to fix the underlying cause.

To post, read, or answer a question, visit our forums. We look forward to hearing from you!

January 1, 2011


Future Memories – Part 1: Phase Change Memory
By Christopher Henderson

This article is the first in a series of articles on new memory technology. As we quick approach the limits of scaling in traditional DRAM and Flash memories, new memory technologies will be needed if we wish to continue creating smaller, more feature-rich electronics. In this first segment, we will discuss Phase Change Memory. In future issues we will also cover resistive RAM, several quantum magnetic devices, carbon nanotubes, and molecular memories. One of the big problems with scaling today’s flash and DRAM memories further is the limit on charge storage. Cell sizes are approaching the point where the amount of charge stored in a single DRAM or Flash memory cell is down into the thousands of electrons. At this level, leakage, process variation, variation in the application, retention times, and a host of other variables become problematic. These problems will likely limit future scaling below 20nm. There are several technologies that have the potential to permit scaling beyond this point. We will discuss one of the leading ones, Phase Change Memory, in this issue. Phase Change Memory is one of the most developed replacement technologies.

There are actually production devices on the market from companies like Micron (formerly Numonyx), and Macronix. Phase-change memory is a type of non-volatile computer memory. It is also known as PCM, PRAM, PCRAM, Ovonic Unified Memory, and C-RAM. Phase change memory uses the unique behavior of a chalcogenide glass. With the application of heat produced by the passage on an electric current, this material can be "switched" between two states, crystalline and amorphous. Table 1 shows some of the properties associated with the chacogenide structure. Recent versions can achieve two additional distinct states, effectively doubling its storage capacity. Phase change RAM is one of a number of new memory technologies competing in the non-volatile role with the almost universal Flash memory. Examples of such phase change materials are GeSbTe and AgInSbTe. Micron in particular uses Ge2Sb2Te5 for its phase change memory devices.

Figure 1 shows the cross section cutaway of a phase change memory cell. In this technology developed by IBM and Macronix, the cell uses a common source line for the transistors associated with the two cells. The word line forms the gate connection for the transistor, and the drain connects to the chalcogenide material. The bit line runs perpendicular above the cell, and is used to program the cell by changing the state of the chalogenide material from polycrystalline to amorphous, or vice versa. The smaller the chalogenide bridge is, the less current required to program the cell.

Phase change memory requires high programming current densities, which is a distinct drawback. To program the cell, current densities of greater than 107 A/cm! (compared to 105-106 A/cm! for a typical flash memory cell) are required. This has led to active regions which are much smaller than the driving transistor area. The discrepancy has forced the manufacturers to package the heater and sometimes the phase-change material itself in sublithographic dimensions. This results in additional expensive processing, which is a cost disadvantage compared to Flash.

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Table 1 – Phase Change Memory (PCM) Properties

The contact between the hot phase-change region and the adjacent dielectric is another fundamental concern. The dielectric may begin to leak current at higher temperature, or may lose adhesion when expanding at a different rate from the phase-change material. Phase-change memory is susceptible to a fundamental tradeoff of unintended vs. intended phase-change. This stems primarily from the fact that phase-change is a thermally driven process rather than an electronic process. The thermal conditions that allow for fast crystallization should not be too similar to standby conditions, e.g. room temperature. Otherwise data retention cannot be sustained. With the proper activation energy for crystallization it is possible to have fast crystallization at programming conditions while having very slow crystallization at normal conditions. Probably the biggest challenge for phase change memory is its long-term resistance and threshold voltage drift. The resistance of the amorphous state slowly increases according to a power law, which goes by approximately t0.07 (see Figure 2). This severely limits the ability for multilevel operation (a lower intermediate state would be confused with a higher intermediate state at a later time) and could also jeopardize standard two-state operation if the threshold voltage increases beyond the design value.

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Figure 1 – Cross section cutaway of a Phase Change Memory Cell. 2 cells are shown in the drawing at the left.

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Figure 2 - Graph showing resistance increase as a function of time in a Phase Change Memory cell.

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