ESD Design and Technology
Instructor: Dr. Steven Voldman
Register for Upcoming Courses
|Course Dates | Location||Cost||Pay Via Credit Card|
|February 11-13, 2014 (Tues.-Thurs.) | San Jose, CA, USA||$1,895 $1,795 until Tues. January 21||Add To Shopping Cart|
|Pay Via Purchase Order/Check|
|Please fax the printable registration form for public courses to (505) 858-9813 to Complete Your Order.|
Course Date/Location Request
Refund Policy: If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.
Electrostatic discharge (ESD) costs the semiconductor industry over $4 billion (USD) a year. This problem is likely to grow in the future as smaller devices are susceptible to damage at lower static voltages and latchup under more subtle conditions. Today, circuit designers and process integration engineers must have a fundamental knowledge of device physics and electrothermal behavior of I/O structures in order to develop a process that is robust and can withstand the challenges of today’s varied IC fielding environments. Layout, ESD pulse behavior, semiconductor physics, and device modeling are all required to produce a successful product. The industry needs competent engineers and scientists to help achieve these goals. ESD Design and Technology is a 3 day course that offers detailed instruction on a variety of subjects pertaining to ESD design and technology. This course is designed for every manager, engineer, and technician concerned with ESD at the I/O design or chip level or supplying ESD tools and simulators to the industry.
What Will I Learn By Taking This Class?
The approach of this 3-day intensive ESD Design and Technology training is to teach attendees to develop their own solutions rather than applying pre-defined design receipts. The training is aiming along developing a good understanding about:
- The different ESD events relevant to the ESD design specifications- HBM,CDM, IEC
- The methodologies to develop custom ESD solutions from component to chip-PCB design levels in different semiconductor technologies and for different design applications - digital, RF, mixed signal and high -voltage
- The use of CAD simulation tools to design and optimize new ESD components and circuits
- ESD design and review work flow and how to develop and use ESD design verification rules
- Methods and hardware for ESD testing and product qualification
- Principles and approaches for ESD failure troubleshooting on IC level In addition to the lectures on the above topics, real-time demo and discussions on common problems are planned thus giving the attendees the possibility to interact wit their colleagues and the lecturer, and possibly find solution to their specific design problems.
Participants learn to develop the skills to determine what constitutes a good ESD design, how to recognize devices that can reduce ESD susceptibility, and how to design new ESD structures for a variety of technologies.
- The seminar will provide participants with an in-depth understanding of the ESD failure mechanism, test structures, equipment, and testing methods used to achieve robust ESD resistance in today’s components.
- Participants will be able to gather ESD data, determine how best to plot the data, and make inferences from that data.
- The seminar will identify the major issues associated with ESD and explain how they occur, how they are modeled, and how they are mitigated.
- The seminar can be offered with several textbooks that cover the topic of ESD in much greater detail. The course author is a recognized expert in the field and has written the definitive textbook series on ESD.
- Participants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.
- Participants will be able to knowledgeably design ESD structures that are appropriate to assure the robustness of a component.
- Participants will be able to identify appropriate tools to purchase when starting or expanding ESD test capabilities.
The scaling of semiconductor devices from sub-micron to nanometer dimensions is driving the need for understanding the design of electrostatic discharge (ESD) circuits, and the response of these integrated circuits (IC) to ESD phenomena.
ESD Circuits and Devices provides a clear insight into the layout and design of circuitry for protection against electrical overstress (EOS) and ESD. With an emphasis on examples, this text:
- explains ESD buffering, ballasting, current distribution, design segmentation, feedback, coupling, and de-coupling ESD design methods;
- outlines the fundamental analytical models and experimental results for the ESD design of MOSFETs and diode semiconductor device elements, with a focus on CMOS, silicon on insulator (SOI), and Silicon Germanium (SiGe) technology;
- focuses on the ESD design, optimization, integration and synthesis of these elements and concepts into ESD networks, as well as applying within the off-chip driver networks, and on-chip receivers; and
- highlights state-of-the-art ESD input circuits, as well as ESD power clamps networks.
Continuing the author’s series of books on ESD, this book will be an invaluable reference for the professional semiconductor chip and system ESD engineer. Semiconductor device and process development, quality, reliability and failure analysis engineers will also find it an essential tool. In addition, both senior undergraduate and graduate students in microelectronics and IC design will find its numerous examples useful.
This volume is the first in a series of three books addressing Electrostatic Discharge (ESD) physics, devices, circuits and design across the full range of integrated circuit technologies. ESD Physics and Devices provides a concise treatment of the ESD phenomenon and the physics of devices operating under ESD conditions. Voldman presents an accessible introduction to the field for engineers and researchers requiring a solid grounding in this important area. The book contains advanced CMOS, Silicon On Insulator, Silicon Germanium, and Silicon Germanium Carbon. In addition it also addresses ESD in advanced CMOS with discussions on shallow trench isolation (STI), Copper and Low K materials.
- Provides a clear understanding of ESD device physics and the fundamentals of ESD phenomena.
- Analyses the behaviour of semiconductor devices under ESD conditions.
- Addresses the growing awareness of the problems resulting from ESD phenomena in advanced integrated circuits.
- Covers ESD testing, failure criteria and scaling theory for CMOS, SOI (silicon on insulator), BiCMOS and BiCMOS SiGe (Silicon Germanium) technologies for the first time.
- Discusses the design and development implications of ESD in semiconductor technologies.
An invaluable reference for EMC non-specialist engineers and researchers working in the fields of IC and transistor design. Also, suitable for researchers and advanced students in the fields of device/circuit modelling and semiconductor reliability.
By using a combination of instruction by lecture, written text material, problem solving and question/answer sessions, participants will learn practical approaches to the failure analysis process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. Our instructors are internationally recognized experts in their fields and have years of both current and relevant experience. The textbooks offer hundreds of pages of additional reference material participants can apply during their daily activities.
Dr. Steven H. Voldman
Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge protection in semiconductor chips. His IEEE Fellow citation is for "contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology." He received his B.S. in Eng. Science from Univ. of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Eng. Physics (1986) and a Ph.D EE (1991) from Univ. of Vermont under IBM's Resident Study Fellow program. Dr. Voldman was a member of the semiconductor development of IBM for 25 years. He was a member of the IBM’s Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS and Silicon Germanium, RF CMOS, RF SOI, smart power technology development and image processing technology teams. In 2007, Voldman joined the Qimonda Corporation as a member of the DRAM development team, and reporting to Qimonda Europe working on 70, 58, 48 and 32 nm CMOS DRAM technology. He was responsible for ESD technology strategy, ESD and latchup design manuals, and ESD design working on ESD protection in 512 Mb, 1 Gigabit, and 2 Gigabit DRAM products. In 2008, Voldman worked as a full time ESD consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) supporting ESD and latchup development for 45 nm CMOS technology and a member of the TSMC Standard Cell Development team in Hsinchu, Taiwan. In 2009 to 2011, Steve was a Senior Principal Engineer working for the Intersil Corporation working on analog, power, and RF applications in RF CMOS, RF Silicon Germanium, and SOI. In Intersil Corporation, Steve was responsible for ESD corporate strategy, ESD CAD development, ESD parameterized cell development, latchup, documentation development, ESD design reviews, and wide range of product development in analog, power, and mixed signal applications.
Dr. Voldman was chairman of the SEMATECH ESD Working Group, to establish a national strategy for ESD in the United States; this group initiated ESD technology benchmarking strategy, test structures and commercial test system strategy. At SEMATECH, he was responsible for establishing collaboration between the ESD Association and the JEDEC standards development, as well as launching the first TLP standard working group. He is a member of the ESD Association Board of Directors, ESDA Education Committee, as well ESD Standards Chairman for TLP and VF-TLP testing. Dr. Voldman was also the first chairman of the ESDA ESD Technology Roadmap committee and co-established the ESD Technology Roadmap in 2005. In 2005, he was the Subcommittee Chairman for both the Latchup Sub-committee for the International Reliability Physics (IRPS) and the EOS/ESD Symposium, the ESD Chairman for the International Physical and Failure Analysis (IPFA) Symposium, and presently serving on the technical program committees for the Taiwan ESD Conference (T-ESDC) 2010 in Taiwan, and ICSICT 2010 in China. Steve has provided tutorials on ESD, latchup, failure mechanisms, and RF ESD devices to the IRPS, EOS/ESD, T-ESDC, BCTM, IPFA, ASICON (China), and ICSICT (China). He was the recipient of the ESD Association Outstanding Contribution Award in 2007.
Dr. Voldman is an author of the six books ESD: Physics and Devices, ESD:Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, and ESD: Failure Mechanisms and Models, ESD: Design and Synthesis as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design, and a chapter contributor to new text Nanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In 2011, Dr. Voldman is presently writing new ESD text books to extend the John Wiley and Sons Ltd ESD book series to be released at a future date.
In the ESD Association, Voldman initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 35 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, and China. He also provides tutorials internationally on ESD protection. Dr. Voldman has written over 150 technical papers between 1982 and 2007. He is a recipient of over 215 issued US patents. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents; and has also founded a limited liability corporation (LLC) consulting business supporting ESD design, teaching, patents and patent litigation. S. Voldman served as the ESD expert witness for Acer vs Hewlett Packard, as well as other patent litigation cases.