Copper Wire Bonding Technology and Challenges
Instructor: Steve Groothuis
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The drive to reduce costs in semiconductor and integrated circuits remains a key challenge for the industry. For example, many of today’s ICs use expensive gold wiring. As a result, the industry is pushing to use copper wires and copper pillar bumping in an increasing array of applications. This has created a number of challenges related to the bonding and packaging of these components. Copper Wire Bonding Technology and Challenges is a 2-day course that offers detailed instruction on the technology issues associated with today’s semiconductor packages. We place special emphasis on current issues like bond formation, bumping, and tools for package analysis. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.
By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.
What Will I Learn By Taking This Class?
Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:
- Basic Semiconductor Wire Bonding Metallurgy. Participants will study the phase diagrams that are most useful to IC packaging and learn about basic metallurgy topics such as melting, solidification, intermetallic compounds, oxidation, corrosion and welding.
- Important Copper Alloy Systems in IC Packaging. The course presents metallurgical principles with selected alloy and materials systems that are key to the understanding and analysis of semiconductor (IC) packaging assembly and reliability.
- IC Mounting and Bonding. Participants will learn about alloy mounts and Ag-filled die attach. Additionally, they'll learn about wire bonding, flip-chip soldering, and package mounting. Phase diagrams are used as a basis for examining what solid solutions, phases, and intermetallic compounds (IMC) should be expected in an assembled or PC-board mounted IC package, and where the phases should form in a well-built system. Oxidation/reduction potentials are the first steps toward resolving corrosion resistance issues, either in package design or failure analysis. Since assembly techniques join metals by soldering or thermo-compression/thermo-sonic methods, the behavior of melting and solidification and the formation of solid solutions and IMCs, as read from the phase diagrams, is presented as an important predictive and diagnostic tool.
- Reliability and Environmental Tests. The last part of the class brings together the basic principles and selected alloy systems to analyze the results of reliability testing, interpret the observed failure modes to identify root causes, and predict behavior for materials or process changes implemented to lower costs and/or improve reliability. The course covers moisture tests, thermomechanical tests, electromigration, and failure analysis methodology.
- At the end of the course, participants will know how to read and interpret phase diagrams for melting and solidification behavior.
- They will also know the compositions of the solids and intermetallic compounds that should form.
- Participants should be able to predict and identify potential corrosion products from environmental testing and field failures. They should also know how to interpret failure analysis results.
- Finally, participants will gain methods to apply these principles to process and material changes to lower cost and produce increased reliability for IC packaging.
- Participants will be able to make decisions about how to construct and evaluate new packaging designs and technologies.
- The participant will see several case studies associated with copper wire bonding.
By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.
Mr. Steve Groothuis, M.S. Physics
Steve Groothuis received a Bachelor’s in Physics (1983) from Michigan State University and Masters in Physics (1991) from the University of Texas. He began performing semiconductor package development, design, testing, and simulation in the Central Packaging Group, Texas Instruments in Dallas in 1983 as a Group Member of the Technical Staff. Prior to leaving TI, he managed the engineering staff in TI's Advanced Semiconductor Packaging Lab. In 1997, he was a Multiphysics Industry Specialist for ANSYS, Inc., defining Computer-Aided Engineering simulation software market plans, strategic accounts management, electronics packaging, MEMS device simulation initiatives, and product development for the electronics industry. From 2000-2008, he was with Micron Technology in positions from Senior Package Engineer in the Assembly and Packaging Department to Technology CAD and Analysis Manager in the Process RD Department at Micron Technology. His responsibilities included working with device and process simulations for new cell designs, supporting most aspects of semiconductor package simulations, and assessing new technology.
Currently, Mr. Groothuis is a Principal Consulting Engineer with SimuTech Group, Inc. He is actively involved in developing and winning new business opportunities for Finite Element Analysis (FEA) and Computational Fluid Dynamics (CFD) consulting projects. His efforts are focused on vertical markets such as Microelectronics, Semiconductor Packaging, Wafer Fabrication, NEMS/MEMS, Nanotechnology, Solar Energy, Wind Energy, and Consumer Electronics.
He has published over 30 papers at various conferences in semiconductor packaging, reliability, and numerical analysis. Mr. Groothuis is a Senior Member of the IEEE and has participated in ASME and JEDEC standards committees.