IC Packaging Technology and Metallurgy

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Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The industry is also pushing to use semiconductor devices in an increasing array of applications. To accomplish this, the industry is also driving prices down. This has created a number of challenges related to the packaging of these components. IC Packaging Technology and Metallurgy is a 3-day course that offers detailed instruction on the technology issues associated with today’s semiconductor packages.

What Will I Learn By Taking This Class?

We emphasize current package technology issues like lead-free solders, low-k dielectrics, and tools for package analysis. Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments. Click here to view a full, printable course outline.

  1. Packaging Technology Overview. Participants study the packaging portion of the International Technology Roadmap for Semiconductors (ITRS) to learn about the issues facing packaging technology. They learn why use conditions have become critical to semiconductor packaging for today’s designs.
  2. Current Issues. Participants learn the issues surrounding the introduction of low-k materials on the die and their impact on packaging, the introduction of lead-free solders and their impact on packaging, and the impact of packaging when deciding between “system on a chip” and “system in a package” configurations.
  3. Thermal Simulations. Participants learn the fundamentals of reliability for packaging. They also study the tools and techniques used for analyzing problems with packaging.
  4. Future Semiconductor Packages. Participants discuss the future of semiconductor packaging. This includes technologies that are currently being introduced, like Microelectromechanical Systems (MEMS), nano-scale devices, and devices that will be used in the approaching convergence of electronics and biology.

This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.

By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.

Course Objectives

  1. The seminar will provide participants with an in-depth understanding of semiconductor packaging technology and its technical issues.
  2. Participants will understand the issues behind packaging technology and why we are facing certain predicaments.
  3. The seminar will identify the key issues related to the continued growth of the semiconductor industry. This includes the need for materials that can withstand high power dissipation and materials that can mitigate the increasing fragility of the die because of low-k dielectrics.
  4. Participants will understand how package reliability, power consumption and device performance are interrelated.
  5. Participants will be able to make decisions about how to construct and evaluate new packaging designs and technologies.
  6. The participant will also be introduced to polymers, solders, and a host of materials being considered for advanced packaging.

Instructional Strategy

Our courses are dynamic. We use a combination of instruction by lecture, problem solving, and question/answer sessions to give you the tools you need to excel. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. The course notes offer hundreds of pages of reference material that participants can apply during their daily activities.

Our instructors are internationally recognized experts. Our instructors have years of current and relevant experience in their fields. They're focused on answering your questions and teaching you what you need to know.

Instructor Profile

Dr. Roger Stierman

roger.stierman

Dr. Roger Stierman is an independent consultant who focuses on packaging issues and analysis techniques. Roger received a B.S. in Physics from Loras College and M.S. and Ph.D. degrees in Metallurgy from Iowa State University. During his 25-year career at Texas Instruments, he developed processes for semiconductor package assembly and characterized semiconductor packaging materials such as die attach, mold compounds, polymer overcoats, wire bond and flip chip connections, flip chip underfills, and package-to-PWB attachment. As manager of the Semiconductor Packaging Lab, he delivered training for physical failure analysis methods including precision cross-sectioning, SEM/EDS, X-Ray, tensile and 4-point bend testing, microhardness, RIE/ICP etching, ion milling and laser decapsulation. Currently, he is a consultant on semiconductor packaging failure analysis for Omniprobe Inc.

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