Wafer-Level Chip Scale Packaging
Instructor: John Briar
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Semiconductor packaging developments continue to proceed at an incredible pace. A relatively new packaging technology making inroads in electronic systems is wafer level chip scale packaging (WLCSP). In WLCSP, the bonding, testing, and bumping is performed at the wafer level. This can lead to faster, more power-efficient products, and products compatible with smaller form factors. WLCSP is a marked departure from conventional packaging techniques, so the tools, technologies, and processes are quite different. This has created a number of challenges related to the packaging of these components. Wafer Level Chip Scale Packaging Technology is a 2 day course that offers detailed instruction on the technology issues associated with today’s WLCSP semiconductor packages. We place special emphasis on current issues like conductive adhesives, gold, copper, nickel-gold materials, stud bumping, and through-silicon vias (TSVs). This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.
What Will I Learn By Taking This Class?
By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.
Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:
- WLCSP Packaging Technology Overview. Participants study the fundamental materials and processes to learn about the issues facing packaging technology. They learn why wafer level processes have become critical to semiconductor packaging for today’s designs.
- Solder Joint Issues. Participants learn the issues surrounding the introduction of different soldering materials and their impact on packaging, thinned wafers, bonding, and TSVs.
- Wafer Thinning and Bonding. Participants learn the fundamentals of wafer thinning and bonding for packaging. They also study the tools and techniques used for low temperature bonding during packaging.
- TSVs. Participants discuss this new form of interconnect which has generated considerable interest in recent years. They will understand the strengths and weaknesses of using TSVs in WLCSP applications.
- The seminar will provide participants with an in-depth understanding of wafer level chip scale packaging technology and its technical issues.
- Participants will understand the issues behind packaging technology and why we are facing certain predicaments.
- The seminar will identify the key issues related to the continued growth of the semiconductor industry. This includes the need for bonding, stud bumps, TSVs, and wafer bonding.
- Participants will understand how package reliability, power consumption and device performance are interrelated.
- Participants will learn about thin wafer handling and bonding.
- Participants will be able to make decisions about how to construct and evaluate new packaging designs and technologies.
- The participant will also be introduced to thermal management for advanced packaging.
- Lead-Free Components, PCB, and Soldering
- Flip-Chip Wafer Level Processing Technologies with (Tin-Lead and Lead-Free) Solders
- Solder Bumps
- Wafer Bumping Methods
- Solder-bumped Flip Chip on PCB/Substrate Assembly Process
- Underfill Encapsulants
- Solder Joint Reliability of Flip-Chip WLCSP Assemblies
- Flip-Chip WLP Technologies with Conductive Adhesives (Lead-Free)
- Conductive Adhesives – ACA, ACF, etc.
- Au, Cu, NiAu, and Au-stud Bumps
- Materials, Process, and Reliability of WLCSP on PCB with ACF
- Au-Stud Bumped WLCSP with ACF on PCB
- Au-Stud Bumped WLCSP Diffused on Au-Plated PCB and Flex
- Reliability of Solderless Flip-Chip Assemblies
- 3D IC Integration and WLP
- TSVs for Interposers, Stacked chips
- TSV Processes (Etching or Laser Drilling, Dielectric Deposition, Barrier/Seed Metal Plating, Filling, Polishing
- Via First TSV
- Via Last TSV
- Thin Wafer Handling
- Low-Temperature Bonding (LTB)
- W2W LTB
- C2W LTB
- Solder Microbumping and Assembly
- Thermal Management of 3D Stacked Chips
- Embedded Wafer Level Packaging
By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.
John Briar is currently the Business Development Director for MobileIron, a company providing mobile device management. Prior to MobileIron he was the Packaging Development Manager at Micron Technology. At Micron, he was responsible for working with internal and external customers to develop new Semiconductor packaging solutions for NAND and DRAM devices and markets, maintaining the company wide 5 year strategic packaging roadmap for NAND products. He also developed, qualified, and managed subcontract assembly sites in Asia for Micron product lines including DRAM, NAND, Micro SD, and Stacked Die TSOP and LGA/BGA packages. He also worked to develop external bumped interconnect strategy and capability for TSV and TSV die to die lead free interconnect schemes. He has also held positions at A-A Engineering Consultants, Advanpack Solutions, STATS-ChipPAC, Amkor and Compaq Computer. John is a graduate of the University of Central Florida.