Wafer Fab Processing
Instructor: Jim A. Fraser
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|Course Dates | Location||Cost||Pay Via Credit Card|
|February 18, 2014 (Tues.) | San Jose, CA, USA||$795 $695 until Tues. January 28||Add To Shopping Cart|
|Pay Via Purchase Order/Check|
|Please fax the printable registration form for public courses to (505) 858-9813 to Complete Your Order.|
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Refund Policy: If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.
Due to countless breakthroughs and developments in wafer fab processing, today's semiconductor wafer fabrication process contains some of the most intricate procedures developed by humankind. Semitracks' 1-day Wafer Fab Processing course looks in-depth at the semiconductor manufacturing process and individual processing technologies.
What Will I Learn By Taking This Class?
By focusing on the basics of each processing step and the issues surrounding next-generation devices, you'll learn why certain techniques are preferred over others. Additionally, you'll learn basic but powerful information about the wafer fabrication process.
This skill-building series is divided into three segments:
- Basic Semiconductor Wafer Processing Steps. Each processing step addresses a specific need in IC creation. You'll learn the fundamentals of each processing step and why it is used in the industry today.
- The Evolution of Each Processing Step. It is important to understand how wafer fab processing came to the point where it is today. You'll learn how each technique has evolved for use in previous and current generation ICs.
- Current Issues in Wafer Fab Processing. You'll learn how wafer fab processing equipment is increasingly constrained by physics and materials science. You'll also learn how new materials in the fabrication process may create future problems for silicon wafer manufacturing.
This course is a must for every manager, engineer, and technician working in the semiconductor industry, using semiconductor components, or supplying tools to the industry. Our instructors work hard to explain how semiconductor wafer processing works without delving heavily into the complex physics and mathematical expressions that normally accompany this discipline.
- The seminar will provide participants with an in-depth understanding of the semiconductor fabrication industry's technical issues.
- Participants will understand the fundamental wafer fab processing steps.
- The seminar will identify the key issues related to each processing technique. Additionally, participants should be able to describe how wafer fabrication technique limitations affect the continued scaling of the semiconductor industry.
- Through working sample problems, participants will gain hands-on knowledge of wafer fab processing fundamentals.
- Participants will be able to identify the features and principles associated with each major processing step, including chemical vapor deposition, ion implantation, lithography, and etching.
- Participants will understand the interrelations of processing, reliability, power consumption, and device performance.
- Participants will be able to decide how to construct and evaluate processing steps for CMOS, BiCMOS, and bipolar technologies.
- Raw Silicon Wafers – This includes information on crystal growth, purification techniques, markings, and other parameters.
- Ion Implantation – This section covers high voltage and high current implanters, effects like channeling, heating, dopant spreading, and techniques for modern ICs.
- Thermal Processing – This section includes standard oxidation and diffusion as well as information on rapid thermal annealing.
- Contamination Monitoring and Control – This section covers methods for contamination control like HEPA filters and purification techniques for water, gases, and chemicals. It also covers wafer inspection techniques.
- Wafer Cleaning and Surface Preparation – This section includes material on chemical and mechanical cleaning processes, as well as strategies for wafer cleaning.
- CVD – This section tackles the various types of chemical vapor deposition including low pressure, atmospheric pressure, and plasma-enhanced CVD. It provides an overview of epitaxial growth, and thin-film deposition.
- PVD – This section covers both evaporation and sputtering techniques used for deposition.
- Lithography – This section covers existing lithography technologies and provides insight into the upcoming transition to extreme ultraviolet lithography. The section provides an overview of light behavior, resists for lithography, and reticle enhancement technologies like double patterning, sub-resolution assist features, and phase shift masks.
- Etch – This section covers both dry and wet techniques for etching. It includes an overview of reactive ion etching and the variables involved with determining the structure and topography of an etch.
- CMP – This material covers the basics of chemical mechanical planarization, including the equipment and slurries. It also covers issues associated with loading.
- Cu Interconnect and low-k Dielectrics – This section covers techniques for depositing copper and low-k dielectrics. It covers the damascene and dual damascene processes used for patterning copper. This section also provides an overview of common low-k dielectric materials and the process integration involved with their use.
- Leading Edge Technologies and Techniques – e.g.
- ALD – Atomic Layer Deposition is used for transistor gates, and copper liners
- high-k gate and capacitor dielectrics – This includes materials like hafnium oxides and silicates, as well as tantalum pentoxide and barium strontium titanate for DRAM capacitors.
- metal gates – This includes materials like tantalum nitride, titanium nitride, and alloys that include aluminum and silicon.
- SOI – This includes techniques for making silicon on insulator wafers, as well as advantages and disadvantages of the substrate.
- strained silicon – This includes information on the stress liners and channel materials used to improve transistor mobility.
- plasma doping – This gives an overview of a newer technique to introduce dopants into ultra-shallow junctions.
Our courses are dynamic. We use a combination of instruction by lecture, problem solving, and question/answer sessions to give you the tools you need to excel. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. The course notes offer hundreds of pages of reference material that you can apply during your daily activities. Additionally, the opportunity to work through sample problems under the guidance of an expert instructor allows you to cement the concepts you learn through hands-on implementation.
Our instructors are internationally recognized experts. Our instructors have years of current and relevant experience in their fields. They're focused on answering your questions and teaching you what you need to know.
Jim Fraser received a Bachelor’s degree in Physics from McGill University in Montréal, Québec, Canada. He has 22 years experience in semiconductor manufacturing, at Nortel Networks and STMicroelectronics. As a Process Engineer, Process Engineering Section Manager, and then Process/Device Engineering Manager, he has worked directly and intimately with CMOS and BiCMOS wafer fab processes. He has taught semiconductor manufacturing technology at Algonquin College and most recently at the University of Ottawa in Ottawa, Ontario.