Instructors: Dr. John Suehle and Dr. Jeffrey Gambino

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Course Overview

Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing, and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. Analysis and experimentation is now performed at the wafer level instead of the packaging level. This requires knowledge of design of experiments, testing, technology, processing, materials science, chemistry, and customer expectations. While reliability levels are at an all-time high level in the industry, rapid changes may quickly cause reliability to deteriorate. Your company needs competent engineers and scientists to help solve these problems. Reliability and Characterization Challenges for Advanced Semiconductor Devices is a 1-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and characterization. This course is designed for every manager, engineer, and technician concerned with reliability in the semiconductor field, using semiconductor components, or supplying tools to the industry.

Seminar Objectives

1. The seminar will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment, and testing methods used to achieve today’s high reliability components.
2. Participants will be able to gather data, determine how best to plot the data, and make inferences from that data.
3. The seminar will identify the major failure mechanisms and explain how they are observed, modeled, and eliminated.
4. Participants will be able to identify basic test structures and how they are used to help quantify reliability on semiconductor devices.

Course Outline

1. Introduction to Reliability
   1. Basic Concepts
   2. Definitions
   3. Historical Information
2. Distributions and Their Use in Reliability
   1. Normal Distribution
   2. Lognormal Distribution
   3. Weibull Distribution
   4. Exponential Distribution
   5. Which Distribution Should I Use?
3. Die-Level Failure Mechanisms
   1. Time Dependent Dielectric Breakdown
      1. Basic Concepts
      2. Soft Breakdown
      3. Hi-K Materials
      4. Cu-Low-K Issues
   2. Hot Carrier Damage/NBTI
   3. Electromigration
      1. Aluminum/SiO2
      2. Copper/Low-K
   4. Stress Induced Voiding/Stress Migration
4. Package Level Mechanisms
   1. Moisture/Corrosion
   2. Thermo-Mechanical Stress
   3. Thermal Stress/Cycling
5. Test Structures and Test Equipment
   1. Test Structures
      1. Parametric Test Structures
      2. Reliability Test Structures
      3. Self-Stressing Test Structures
   2. Test Equipment
      1. Packaged Part Testing
      2. Wafer Level Testing
6. Developing Screens, Stress Tests, and Life Tests
7. Future Reliability Challenges

The continued scaling of gate dielectric thickness has resulted in increased leakage current and shrinking reliability margins. Designers must balance circuit performance with device reliability. The introduction of high-k dielectric materials to reduce gate leakage current presents significant challenges for electrical and reliability characterization. Bulk trapping complicates electrical measurements, and wear-out mechanisms are not yet understood. An overview of thin gate oxide reliability will be presented and issues relating to high-k gate oxide reliability will be discussed.

The scaling of transistors exacerbates hot carrier effects. One particularly difficult challenge is overcoming the effects of Negative Bias Temperature Instability (NBTI), and more recently, Positive Bias Temperature Instability (PBTI). Both NBTI and PBTI can degrade the performance of the p-channel transistor. Boron penetration from the polysilicon gate strongly affects NBTI. Both are also difficult to combat through standard processing techniques.

To improve IC performance, copper metallization and Low-K dielectrics are routinely used in advanced processes. Copper metallization exhibits different electromigration, stress voiding, and corrosion behavior than traditional aluminum-based interconnect systems. The mechanical, thermal, and electrical issues due to copper and its integration with Low-K dielectrics will be discussed. Low-K dielectrics exhibit inferior thermal, mechanical, and dielectric breakdown characteristics compared to traditional silicon dioxide and silicon nitride-based materials.

Instructor Profiles

Dr. John Suehle

Dr. Suehle received his B.S. (1980), M.S. (1982), and Ph.D. (1988) in electrical engineering from the University of Maryland, College Park. In 1981 he received a Graduate Research Fellowship with the National Institute of Standards and Technology (NIST), Gaithersburg, MD. Since 1982 he has been working in the Semiconductor Electronics Division at NIST where he is leader of the Advanced MOS Device Reliability and Characterization Project. His research activities include failure and wear-out mechanisms of semiconductor devices, micro-electro-mechanical-systems (MEMS), and molecular electronic devices. Dr. Suehle has published over 100 technical papers or conference proceedings and holds five U.S. patents. He has also presented tutorials on thin oxide reliability at the International Reliability Physics Symposium (IRPS), the IEEE Integrated Reliability Workshop (IRW), the University of Maryland, the University of Delaware, and the University of New Mexico. Dr. Suehle has served on or is currently serving on technical program committees of the International Electron Device Meeting (IEDM), IRPS, IRW, and the Symposium on Plasma and Process Induced Damage (P2ID). Dr. Suehle serves as the chairman of the Oxide Integrity Working Group of the EIA/JEDEC JC 14.2 Standards Committee responsible for developing national standard test procedures for wafer-level reliability. He is a senior member of the IEEE.

Dr. Jeffrey Gambino

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM's manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents.