Defect-Based Testing

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Because today's application-specific ICs and microprocessors can contain over 100 million transistors, traditional stuck-at-fault (SAF) defect modeling is a poor model for defects. Other models and strategies are required to catch today's killer defects on integrated circuits. Semitracks' 2-day Defect-Based Testing short course offers detailed instruction on electrical behavior and test strategies for integrated circuits.

What Will I Learn By Taking This Class?

We place special emphasis on electrical behavior, fault models, and test techniques. By focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior, participants will learn how to design, write, and implement test strategies to catch defects.

The skill-building series is divided into four segments:

  1. Electrical Behavior of Defects. Participants learn how open circuits, resistive vias, shorts, and transistor variations affect the electrical behavior of the individual transistor, gate elements, and larger blocks.
  2. Fault Models for Defect-Based Testing. Participants learn about the historical underpinnings of the stuck-at-fault (SAF) model. They also learn about other testing models, including IDDQ testing, at-speed testing, and delay testing.
  3. Production Test Methods. Participants learn about standard digital testing, SAF testing, IDDQ, timing, low voltage tests, and other types of stress tests. They explore the strengths and weaknesses of each test type.
  4. The Economic and Quality Impact of Defect-Based Testing. Participants learn how defect-based testing can improve test economics. They also study the impact on quality and reliability.

Course Objectives

  1. The seminar will provide you with an in-depth understanding of defect-based testing and its technical issues.
  2. Participants will understand the basic concepts of test economics, yield, test time and the cost of test. They also learn how defect-based testing can reduce the possibility of failures in the field.
  3. The seminar will identify underused test techniques like IDDQ and Very Low Voltage (VLV) that can successfully find defects that are difficult to catch with conventional methods.
  4. The seminar offers the opportunity to discuss specific test problems with our expert instructors.
  5. Participants will be able to identify basic and advanced principles of defect-based testing.
  6. Participants will understand how to overcome some of the limitations of quiescent power supply current (IDDQ) testing with regards to leading edge products.
  7. Participants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.
  8. The seminar will introduce fundamental and advanced principles for extending defect-based testing to future designs.
  9. Participants will learn about the defect-based testing tools on the market today.

Course Outline


Course Outline


Instructional Strategy

Our courses are dynamic. We use a combination of instruction by lecture, problem solving, and question/answer sessions to give you the tools you need to excel in the defect-based testing process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. The course notes offer hundreds of pages of reference material that you can reference and apply during your daily activities.

Our instructors are internationally recognized experts. Our instructors have years of current and relevant experience in their fields. They're focused on answering your questions and teaching you what you need to know.

Instructor Profiles

Christopher Henderson, President of Semitracks, Inc.

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Christopher Henderson received his B.S. in Physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Chris is the president and one of the founders of Semitracks, Inc., a United States based company that trains professionals in the semiconductor industry. He also teaches courses in failure analysis, reliability, and semiconductor technology. From 1988 to 2004, he worked at Sandia National Laboratories as a Principal Member of Technical Staff in the Failure Analysis Department and Microsystems Partnerships Department. His job responsibilities have included failure and yield analysis of components fabricated at Sandia’s Microelectronics Development Laboratory, research into the electrical behavior of defects, and consulting on microelectronics issues for the DoD. Chris has published over 20 papers at various conferences in semiconductor processing, reliability, failure analysis, and test. He has received two R&D 100 awards and two best paper awards. Prior to working at Sandia, Chris worked for Honeywell, BF Goodrich Aerospace, and Intel. Chris is a member of IEEE and EDFAS (the Electron Device Failure Analysis Society).

Michael Bruce, Ph.D.

Dr. Michael Bruce received a B.S. and Ph.D. in Physics from the University of Texas at Austin. After a post-doctoral at Indiana University, he joined Advanced MicroDevices, Inc. in 1995. He now has over 15 years experience in failure analysis and design debug of microprocessors. He helped pioneer the backside failure analysis field with development of optical techniques like RIL/SDL and single-element Time Resolved Emission. Dr. Bruce holds 74 patents and has published numerous papers related to failure analysis and design debug, including a best paper and an outstanding paper at ISTFA for RIL and SDL, respectively. He has chaired and given many tutorials at IRPS, ISTFA, and IPFA, as well as given many lectures at universities and technical seminars. He currently works as an independent consultant, helping customers understand and implement new FA technologies.

Robert Aitken, Ph.D.

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Dr. Aitken has spent the last 15 years working on various aspects of IC design for testability. His current responsibilities include design and test methodology for Artisan's Libraries (Artisan is now a part of ARM Ltd). He has worked in a variety of areas relating to test, including test synthesis, fault modeling, IDDQ testing, and fault diagnosis, as well as contributing to numerous proprietary and/or patented technologies for Agilent's IC business. Additionally, Dr. Aitken has published over 40 technical papers on testing and diagnosis and received the best paper award from the International Test Conference in 1992. He holds a Ph.D. from McGill University in Canada. In addition to being a member of the IEEE and an associate editor of IEEE Transactions on Computer-Aided Design, Dr. Aitken serves on several program committees, including that of International Test Conference. He has also served on the executive committee of the International Conference on CAD and the International Test Synthesis Workshop.

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