3D ESD

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This webcast will discuss electrostatic discharge (ESD) in 2.5D and 3D multi-chip systems. With the desired for high bandwidth, performance, and density, there is tremendous industry growth in this field. The new “3-D chip paradigm” extends into chip architecture; as a result it influences chip floor planning, placement, and integration. Since the “3D chip paradigm” affects chip architecture, electrostatic discharge (ESD) and latchup are influenced. ESD design, placement, electronic design automation (EDA), checking, verification, integration, test, and manufacturing assembly issues will be highlighted in this webcast.

The webcast will review where we have been in the past, and where we are in the present, and where we are going into the future. The early development of active chip carriers, and three-dimensional systems will be first discussed, as well as the questions, paradigms, problems, patents, and innovations. Multi-chip semiconductor chip implementations, with and without “through silicon vias” (TSV) will be discussed from an ESD and latchup perspective, highlighting advantages, disadvantages, and opportunities for innovation. With the new 3-D multi-chip structures, new ESD paradigms exist in the area of ESD design, simulation, testing, standards, and handling in both manufacturing and final test.


Webinar Outline

  1. Multi-chip Structures and the Paradigm Shift
  2. Early Three Dimensional (3-D) Structures
  3. 2.5 D Multi-chip Systems
  4. 3 D Systems
    1. Through Silicon Vias (TSV)
  5. JEDEC Wide I/O Footprint and ESD
  6. ESD in 3-D
    1. ESD Issues, Questions and Paradigms
    2. ESD Architecture – Power Grids
    3. ESD Architecture - ESD Power Clamps
    4. Electronic Design Automation (EDA)
  7. Summary and Conclusions

Instructor Profile

Dr. Steven H. Voldman

steve.voldman

Dr. Steven H. Voldman is an IEEE Fellow for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He was the recipient of the ESD Association Outstanding Contribution Award in 2007. He received his B.S. in Eng. Science from Univ. of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Eng. Physics (1986) and a Ph.D EE (1991) from Univ. of Vermont under IBM's Resident Study Fellow program.

Dr. Voldman was a member of the semiconductor development of IBM for 25 years. He was a member of the IBM’s Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS and Silicon Germanium, RF CMOS, RF SOI, smart power technology development and image processing technology teams. At IBM, Dr. Voldman was involved in DRAM, SRAM, microprocessors, and ASIC development. During this period, he was part of the multi-chip / MLC team for high-end servers. Additionally, in the 1990’s, he was a member of the IBM “CUBE” team that developed early three dimensional (3-D) memory chips, addressing manufacturing, chip architecture, and ESD design issues in 3D implementations.

In 2007, Voldman joined the Qimonda Corporation as a member of the DRAM development team, working on 70, 58, 48 and 32 nm CMOS DRAM technology. In 2008, Voldman worked as a full time ESD consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) supporting ESD and latchup development for 45 nm CMOS technology and a member of the TSMC Standard Cell Development team in Hsinchu, Taiwan. In 2009 to 2011, Steve was a Senior Principal Engineer working for the Intersil Corporation working on analog, power, and RF applications in RF CMOS, RF Silicon Germanium, and SOI.

Dr. Voldman was a member of the ESD Association Board of Directors, ESDA Education Committee, as well ESD Standards Chairman for TLP and VF-TLP testing. Steve has provided tutorials on ESD, and latchup to the IRPS, EOS/ESD, T-ESDC, BCTM, IPFA, ASICON (China), and ICSICT (China). In the ESD Association, Voldman initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 35 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, and many universities in China. He also provides tutorials internationally on ESD protection.

Dr. Voldman is an author of seven books -- ESD: Physics and Devices, ESD:Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, and ESD Basics: From Semiconductor Manufacturing to Product Use, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design, and a new text Nanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. Dr. Voldman also has written an article for Scientific American in October 2002. Dr. Voldman has written over 150 technical papers between 1982 and 2012. He is a recipient of over 242 issued US patents.

In 2007, Dr. Voldman founded a limited liability corporation (LLC) consulting business, Dr. Steven H Voldman LLC, supporting ESD design, teaching, patents, expert witness support, and patent litigation. In his LLC, S. Voldman served as an expert witness for over six cases on DRAM development, semiconductor development, integrated circuits, and electrostatic discharge. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents in Penang, Kuala Lumpur, Johor Bahru, Sri Lanka, and the United States.