Sections
Failure Analysis - Die Level [+/-]
In the past, many problems on semiconductor components could be located and diagnosed using an optical microscope, or a scanning electron microscope. Today's complex integrated circuits can be much more difficult to analyze. This requires a number of defect localization techniques. These techniques include: electron beam techniques, optical beam techniques, photon emission microscopy or light emission, scanned probe techniques, and thermal detection techniques. In addition, one must be able to expose and connect to the area of interest. Chemical unlayering techniques continue to be important; however, a newer tool is rapidly gaining use in this arena - the focused ion beam system.
Courses
- Chemical Unlayering [+/-]
Deprocessing and Sample Preparationare important parts of the failure analysis process. Deprocessing is used to expose underlying layers for examination and characterization andviewing cross-sectioned surfaces. These courses provide information on how to deprocess circuits using chemical etches, plasma and reactive ion etches, and parallel polishing techniques. There is also a course discussing how to cross section circuits. Another course provides information on automated cross-sectioning techniques and TEM sample preparation. A final course provides information on chemical safety.
- Sample Preparation - Part 1
This course provides a introduction to the various types of deprocessing - chemical etching, parallel polishing, cross-sectioning, and plasma/reactive ion etching. It also provides reasons for using one approach over another.
- Sample Preparation - Part 2
This course covers chemical etching techniques for silicon, silicon dioxide, silicon nitride, aluminum, copper and other metals.
- Sample Preparation - Part 3
This course covers parallel polishing techniques for removing interconnect and dielectric layers from an IC to expose underlying interconnect and circuitry.
- Sample Preparation - Part 4
This course covers grinding and polishing techniques for preparing cross section samples.
- Sample Preparation - Part 5
This course covers plasma and reactive etching ion principles, as well as techniques, recipes and issues related to removing both dielectric and metal layers from circuits.
- Sample Preparation - Part 6
This course covers automated techniques for SEM sample preparation, TEM sample preparation, and TEM lift-out.
- Sample Preparation - Part 7
This course covers chemical safety, including personal protective equipment, engineered barriers like fume hoods, chemical storage, handling, and disposal.
- Deprocessing Quiz
This quiz tests the student's knowledge of semiconductor deprocessing techniques.
- Electron Beam Techniques [+/-]
Electron Beam Techniques are a class of fault localization techniques that utilize a scanning electron micoscope. These techniques rely on the interaction of the electron beam with the sample while monitoring an aspect of the electrical behavior of the circuit. These techniques include: charge-induced voltage alteration or CIVA, electron beam induced current or EBIC, resistive contrast imaging or RCI, and several variants of voltage contrast.
- Electron Beam Tools - Part 1
This course covers the various types of voltage contrast used in the analysis of semiconductor devices, including: passive voltage contrast, static voltage contrast, capacitive-coupled voltage contrast, and electron beam probing
- Electron Beam Tools - Part 2
This course covers the physics and applications of Electron Beam Induced Current (EBIC)
- Electron Beam Tools - Part 3
This course covers the physics and applications of a technique related to Electron Beam Induced Current called Resistive Contrast Imaging (RCI)
- Electron Beam Tools - Part 4
This course covers the physics and applications of Charge Induced Voltage Alteration (CIVA).
- Electron Beam Tools - Part 5
This course covers the physics and applications of a technique related to Charge Induced Voltage Alteration called Low Energy Charge Induced Voltage Alteration (LECIVA).
- Electron Beam Techniques Quiz
- FIB [+/-]
The focused ion beam (FIB) system has become an indispensable tool for failure analysis, design debug, and circuit editing. The FIB allows one to make modifications to a circuit and test them before generating new masks for a chip design. This can save millions of dollars in mask and wafer processing costs. The FIB is also used for TEM sample preparation, cross-sectioning, and other types of micromachining activities.
- FIB Analysis
This course provides an overview of focused ion beam technology. Topics discussed in this course include ion column technology, milling, deposition, gas assisted etching, circuit edit, and focused ion beam effects.
- FIB Techniques Quiz
- Inspection [+/-]
Die inspection is arguably one of the most important aspects of any failure analysis job. Die inspection is normally where one first generates an image of the defect, whether it be immediately after opening the sample or preparing the die for backside inspection, or after one or more layers have been removed. Die inspection is performed using three techniques: optical microscopy, infrared microscopy, and scanning electron microscopy. Optical microscopy is performed on the front side of semiconductor devices; infrared microscopy is performed from the backside, and scanning electron microscopy is performed on surface features.
- Infrared Microscopy
This course covers the applications of infrared microscopy for failure analysis. Infrared microscopy allows examination of silicon devices from the backside.
- Optical Microscopy
This course covers the physics and applications of optical microscopy to semiconductor failure analysis. The topics include bright field imaging, dark field imaging, and interference contrast imaging.
- Scanning Electron Microscopy
This course covers scanning electron microscopy for imaging purposes. Topics include the physics of SEM imaging, secondary electron imaging, backscattered electron imaging, and applications.
- Optical and SEM Inspection Quiz
- Light Emission [+/-]
Light Emission Microscopy is a powerful technique for fault localization at the die level. Light Emission Microscopy uses an image intensifier or a cooled semiconductor array camera to detect light emanating from a semiconductor device. Many defects either emit light or cause emission in associated transistors. A variant of light emission called PICA can be used for inferring waveform information on an integrated circuit. Although the technique is quite powerful, interpretation of light emission data can be challenging. The analyst must possess a sound understanding of electrical circuit behavior as well as device recognition skills.
- Light Emission Microscopy - Part 1
This course provides a short introduction to light emission microscopy.
- Light Emission Microscopy - Part 2
This course covers the physics of light emission, including: radiative and non-radiative recombination, and hot carrier effects. The course also covers the topic of spectral light emission.
- Light Emission Microscopy - Part 3
This course covers the two major classes of camera systems used for light emission microscopy: intensified cameras and charged-coupled device (CCD) cameras.
- Light Emission Microscopy - Part 4
This course covers the applications and issues surrounding light emission microscopy. The topics include: what types of gates and bias conditions result in light emission, where light emission is observed, and stimulus techniques.
- Light Emission Microscopy - Part 5
This course covers time resolved light emission, including the original PICA technique and the more sensitive single point detection methods.
- Light Emission Quiz
- Optical Beam Techniques [+/-]
Failure analysts now perform much of the fault localization work from the backside of the device. The complexity of the integrated circuits and the packaging has caused this transition. In order to penetrate the silicon, optical beam techniques are used. They are a class of techniques that rely on the interaction of an optical beam with the active devices or interconnect on the circuit. These include: electro-optical probing, light induced voltage alteration or LIVA, thermally induced voltage alteration or TIVA, optical beam induced current or OBIC, resistive interconnect localization and soft defect localization. The distinguishing feature of these techniques is that they require a scanning optical microscope system, and occasionally, complex stimulus, in the form of a properly chosen or designed vector set.
- Optical Beam Techniques - Part 1
This course covers optical beam induced current (OBIC) and a more sensitive technique that uses constant current biasing called light induced voltage alteration, or LIVA. OBIC is useful for imaging junctions and defects associated with junctions. LIVA is useful for imaging junctions, and defects connected to junctions, including open circuits. Both OBIC and LIVA can be used from the front and back side of the semiconductor.
- Optical Beam Techniques - Part 2
This course covers Seebeck effect imaging. Seebeck effecting imaging is useful for localizing open interconnect, both from the front side and back side of the semiconductor device.
- Optical Beam Techniques - Part 3
This course covers thermally-induced voltage alteration (TIVA). TIVA is useful for localizing shorts and resistance changes from the front side or back side of the semiconductor device.
- Optical Beam Techniques - Part 4
This course covers electro-optical probing techniques, including techniques that use the Kerr effect, the Pockels effect, and the Franz-Keldysh effect. It also covers the laser voltage probe (IDS-2K).
- Optical Beam Techniques - Part 5
This course covers soft defect localization. Soft defect localization is a class of techniques that use laser stimulation and ATE pass-fail status to localize defects. Topics include resistive interconnect localization, identifying timing problems, and design/manufacturing interactions that impact functionality.
- Optical Beam Techniques Quiz
- Scanned Probe Techniques [+/-]
The invention of the scanning tunneling microscope in 1981 has spawned a variety of instruments and techniques that fall under a category called Scanned Probe Techniques. Scanned Probe techniques involve micromachined tips that can be scanned with great precision over the surface of a device. These techniques can be used to look at the topography of a surface, and a variety of other phenomena such as electrical, magnetic, capacitive, thermal, and optical interactions.
- Scanned Probe Techniques
This course covers a class of techniques that use scanned probe tips. The most common of these techniques is the atomic force microscope, but many others exist. This course discusses not only the atomic force microscope, but also scanning tunneling microscopy, scanning capacitance microscopy, magnetic force microscopy, and a new magnetic imaging technique based on a class of sensors called superconducting quantum interfere devices (SQUID).
- SPM Techniques Quiz
- Thermal Detection Techniques [+/-]
Thermal Detection Techniques are a class of techniques used to detect heat-generating defects on semiconductor devices. They are also occasionally used to verify thermal models of semiconductor components. The most popular of the thermal detection techniques are Infrared Thermography, Liquid Crystal Thermography, and Fluorescent Microthermal Imaging. Infrared Thermography is a sensitive, non-contact technique, but it lacks the spatial resolution needed for fine localization on semiconductor dice. Liquid Crystal Thermography has better spatial resolution, but only delineates temperatures above or below a certain temperature. Fluorescent Microthermal Imaging has good spatial resolution and thermal mapping capabilities, but is somewhat more difficult to use.
- Thermal Detection Techniques - Part 1
This section provides an overview of thermal detection techniques. It briefly discusses some of the less known thermal techniques such as the Schlieren technique, photodeflection thermal spectroscopy, thermoreflectance laser probing, internal infrared laser deflection, and the scanning thermocouple probe.
- Thermal Detection Techniques - Part 2
This section covers the basics of blackbody radiation and infrared thermography. Infrared thermography is a non-contact thermal detection technique.
- Thermal Detection Techniques - Part 3
This section covers liquid crystal thermography. It is a real-time temperature technique that allows one to sense regions above the clearing point of a liquid crystal.
- Thermal Detection Techniques - Part 4
This section covers fluorescent microthermal imaging (FMI). FMI uses a temperature-sensitive compound to convert thermal data into visible light. It can be used to generate a temperature map of a semiconductor device.
- Thermal Detection Techniques - Part 5
This section covers several examples using FMI to locate defects and regions of high current and power dissipation.
- Thermal Detection Techniques Quiz
This quiz tests the student's knowledge of the three main thermal detection techniques: Liquid Crystal Hot Spot Detection, Infrared Thermography, and Fluorescent Microthermal Imaging.
Documents
- Chemical Unlayering [+/-]
- Chemical Unlayering
This material contains a discussion of chemical and mechanical deprocessing, including wet chemical etching, reactive ion etching, and parallel polishing. Topics include: chemical deprocessing, mechanical deprocessing, chemical etching, silicon etch chemistry, dieletric removal, decoration etches, decoration stains, metal interconnect, polysilicon etches, gallium arsenide etch chemistry, reactive ion etches, silicon dioxide etches, parallel lapping, die backside polishing.
- Electron Beam Techniques [+/-]
- Electron Beam Techniques
This material discusses various electron beam analysis tools, including: voltage contrast, secondary electron imaging, static voltage contrast, capacitive coupling voltage contrast, passive voltage contrast, electron beam probing, electron beam induced current, resistive contrast imaging, charge induced voltage alteration or CIVA.
- FIB [+/-]
- FIB Technology
This material covers focused ion beam technology. The material covers the physics, instrumentation, and applications of the focused ion beam (FIB) system. Topics include: physics of operation and imaging, FIB of applications and considerations, electrical circuit irradiation effects and countermeasures, future FIB developements.
- Inspection [+/-]
- Inspection
This material provides an overview of Optical and SEM Inspection, including topics such as bright field microscopy, dark field microscopy, Nomarski or interference contrast microscopy, infrared microscopy, scanning electron microscopy, electron beam sample interaction physics, secondary electron imaging, and backscattered electron imaging.
- Light Emission [+/-]
- Light Emission Microscopy
This material discusses Photon Emission Microscopy (also known as Light Emission Microscopy). The topics include photon emission microscopy, theory of light emission from silicon ICs, PEM detectors, spectral analysis of light emission data, spectrometer theory of operation, forward biased pn junctions, reverse biased pn junctions, MOSFETs in saturation, latchup, gate oxide failures, effects of thin dielectric films on transmitted spectra, gate oxide failure example, polysilicon stringer example.
- Optical Beam Techniques [+/-]
- Optical Beam Techniques
Chapter discussing various optical beam tools. Examples of subjects covered are optical beam induced current, light-induced voltage alteration, seebeck effect imaging, thermally-induced voltage alteration, electro-optical probing, laser voltage probe.
- Scanned Probe Techniques [+/-]
- Scanned Probe Techniques
Chapter covering different scanned probe techniques, including scanning probe microscopy, scanning tunneling microscopy, atomic force microscopy, scanning capacitance probe microscope, magnetic current microscopy, lateral force microscopy, scanning near field optical microscopy, superconducting quantum interference, device microscopy.
- Thermal Detection Techniques [+/-]
- Thermal Detection Techniques
Overview of several thermal detection techniques. Topics include blackbody radiation, infrared thermography, liquid crystal, flourescent microthermal imaging, EuTTA compound specifics, image processing, system hardware, photon shot noise, signal averaging, ultraviolet film bleaching, and scanning FMI.
Videos
- Chemical Unlayering [+/-]
- Electron Beam Techniques [+/-]
- Capacitive Coupled Voltage Contrast & Static Voltage Contrast
This video clip describes two electron beam techniques: capactive coupled voltage contrast, and static voltage contrast. Static voltage contrast allows one to observe differences in voltage levels on a depassivated IC, while capacitive coupled voltage contrast allows one to observe changing voltage conditions on a passivated IC.
- CIVA
This video describes Charge-Induced Voltage Alteration and a variant called Low-Energy Charge-Induced Voltage Alteration. THis technique is used to localize open conductors on integrated circuits.
- Electron Beam Probing - Imaging, Setup, & Waveform Acquisition
This video describes how Electron Beam Probing is performed. It describes how to set up the ATE and E-Beam test system, how to obtain a clear image, and how to acquire a waveform from an example IC.
- Resistive Contrast Imaging
This video describes the Resistive Image Contrast (RCI) techinque and shows how to acquire an RCI image.
- FIB
- Circuit Editing & Cross Sectioning
- Inspection
- Optical Microscopy - Parts 1, 2, & 3
- Light Emission [+/-]
- Optical Beam Techniques
- LIVA - Backside, Frontside, & SRAM Example
- Seeback Effect Imaging
- TIVA - Backside SRAM Short
- TIVA - Metal-2 Metal-3 Short
- Scanned Probe Techniques
- Atomic Force Microscopy
- Magnetic Force Microscopy
- Thermal Detection Techniques
- Fluorescent Microthermal Imaging
- Liquid Crystal Thermography
Failure Analysis - Electrical [+/-]
Electrical testing is an integral part of product analysis activities. Most failures or problems manifest themselves as an incorrect electrical condition. This means that the analyst must be able to properly exercise the component to activate the defective condition. Once the defect can be activated, it can be further characterized to help determine the nature of the defect. An electrical condition can give clues as to the cause of the problem. Some troubleshooting techniques work intimately with electrical testing. These include defect localization techniques such as light emission and voltage contrast. Some of the electrical testing concepts that an analyst should be familiar with include: basics of circuit operation, curve tracer/semiconductor parameter analyzer operation, digital troubleshooting, analog troubleshooting, quiescent power supply current, and test equipment. Many of these topics are also covered in the test portion of our website.
Courses
- Troubleshooting [+/-]
This course contains material related to troubleshooting integrated circuits. Troubleshooting is an important part of the failure analysis process, and it is also critical for design debug activities. It covers digital integrated circuit troubleshooting techniques, analog integrated circuit troubleshooting techniques, basic microprocessor troubleshooting techniques, and memory troubleshooting techniques.
- Analog Troubleshooting
This section covers techniques for troubleshooting analog circuits such as voltage references, operational amplifiers, digital to analog and analog to digital converters.
- Digital Troubleshooting
This section covers techniques for troubleshooting basic digital logic. It includes methods for backtracing in combinational logic, locating problems in sequential logic, and identifying hazards in race conditions.
- Memory Troubleshooting
This section covers the test patterns and techniques used to troubleshoot static random access memory, dynamic random access memory, and non-volatile memory.
- Microprocessor Troubleshooting
This section covers a technique used to troubleshoot both microprocessors and microcontrollers. It utilizes a concept called the fault window concept.
- Electrical Analysis [+/-]
Electrical analysis is critical to the success of most failure analysis work. In order to diagnose a problem with an integrated circuit one must be able to first reproduce the electrical failure mode, and second develop a simplified electrical test that will enable analysis using various techniques. This workspace covers basic device operation, curve tracer use, automatic test equipment, and electrical characteristics associated with trapped charge and mobile ionic contamination. It also covers techniques for troubleshooting a variety of microelectronic circuits including digital logic, memories, microprocessors and microcontrollers, and analog circuits. Finally, this section covers tools that can be used to automate the process of troubleshooting.
- Basic Circuit Electrical Behavior
This section covers basic device and transistor operation. It includes a discussion on the parasitic elements associated with the bipolar junction and MOS transistor.
- Electrical Testing - Part 2
This section covers the electrical behavior of defects. It includes discussions on bridging defects, open circuit defects, and delay defects.
- Electrical Testing - IDDQ and Test Equipment
This section covers a test technique called quiescent power supply current (IDDQ). It also covers an introduction to automatic test equipment.
- Electrical Testing - Part 4
This section covers the methods and techniques for identifying moisture, mobile ionic contamination, and trapped charge using biased and unbiased bakes.
- Software Aids
This section covers software tools and techniques that can aid in the troubleshooting process. It includes discussions on automatic test pattern generation and fault dictionaries.
- Quiz: Electrical Testing
Documents
- Electrical Analysis [+/-]
- Electrical Testing
This chapter discusses various topics concerning electrical testing. Topics include: basics of circuit operation, discrete devices, transistors, integrated circuits, curve tracer and parameter analyzer operation, quiescent power supply current, parametric tests, timing tests, automatic test equipment, digital circuit troubleshooting, and analog circuit troubleshooting.
Videos
Failure Analysis - Materials Characterization [+/-]
Materials Characterization is occasionally used in failure analysis, and extensively used in yield analysis activities. There are a wide variety of techniques that allow examination of the device surface, as well as the top few microns of a sample. These include techniques like Auger Electron Spectroscopy, which is used for surface analysis, energy dispersive x-ray spectroscopy, which is used for analysis of the top 1 to 5 microns of a sample, Secondary Ion Mass Spectroscopy can be used for both surface analysis and depth profiling, and Transmission Electron Microscopy is used for high resolution imaging of prepared samples.
Courses
- Materials Characterization [+/-]
Materials characterization is an important discipline within the semiconductor manufacturing field. One must be able to identify and characterize topography, vertical structures, aspect ratios, concentrations, dopant distributions, as well as defective conditions and foreign material. Materials characterization can loosely be divided into two groups: imaging techniques and materials analysis techniques.
- Analytical Techniques
This section provides an overview of several materials analysis techniques that are used to characterize semiconductor devices and surface contamination. It includes brief discussions on transmission electron microscopy, energy dispersive X-ray spectroscopy, Auger electron spectroscopy, electron energy loss spectroscopy, ion, infrared, and X-ray analysis techniques.
- Analytical Techniques Quiz
Documents
- Materials Characterization [+/-]
- Analytical Techniques
This discussion on analytical techniques covers such topics as transmission electron microscopy, energy dispersive spectroscopy, wavelength dispersive spectrometry, quantitative X-ray analysis, auger electron spectroscopy, depth profiling, and secondary ion mass spectroscopy.
Videos
- Materials Characterization
Failure Analysis - Package Level [+/-]
As semiconductor packaging becomes more complex, more analysis is required at the package level. There are several techniques that are used frequently for package level analysis. These include: acoustic microscopy, hermetic seal techniques, optical microscopy, particle impact noise detection (or PIND), and x-ray radiography. In addition to these non-destructive techniques, it is also necessary to have techniques to access or expose the die for further analysis. This access may be from the front side or the back side depending on the device and the information required.
Courses
- Package Access [+/-]
An important step in most analysis work is gaining access to the die surface or backside of the silicon. There are a wide variety of package styles and configurations, and as such, there are a variety of decapsulation techniques. This material covers decapsulation and sample preparation techniques for both frontside and backside analysis work.
- Backside Sample Preparation - Part 1
This section covers a number of techniques used for decapping integrated circuits and semiconductor devices. It includes mechanical, chemical, and thermal techniques.
- Backside Sample Preparation - Part 2
This section covers the use of mechanical grinding and polilshing as a backside sample preparation technique. It also covers the use of computer numerically-controlled milling, and reactive ion etching.
- Backside Sample Preparation - Part 3
This section covers the use of the focused ion beam and laser microchemical technique for preparing local areas from the backside.
- Quiz: Package Decapsulation and Backside Sample Preparation
- Package Inspection Techniques [+/-]
Because the package can cover potential problems, one needs techniques for examining the package. These techniques fall into two categories: destructive and non-destructive. Destructive techniques involve removing material or puncturing a device cavity, while non-destructive techniques use electrical, x-ray, magnetic, or acoustic techniques to image structures or observe electrical behavior within the package.
- Package Inspection Techniques - Part 1
This section covers the basics of plastic and ceramic packaging technologies. It includes a discussion of wirebonding, die attach, and package lead-frame construction.
- Package Inspection Techniques - Part 2
This section covers the use of optical imaging for examination of package-related failures.
- Package Inspection Techniques - Part 3
This section covers x-ray radiography and micro-focus x-ray imaging. This technique can identify packaging flaws, contamination, and voids.
- Package Inspection Techniques - Part 4
This section covers scanning acoustic microscopy. This technique can identify interface problems and delaminations.
- Package Inspection Techniques - Part 5
This section covers techniques used to evaluate package cavities. The techniques discussed include: hermetic seal testing, particle impact noise detection, and residual gas analysis.
- Quiz: Package Analysis Techniques
Documents
- Package Access [+/-]
- Package Inspection Techniques [+/-]
- Packaging Testing
Here we talk about package-level testing, including external visual examination, X-ray radiography, hermeticity testing, fine leak hermetic seal testing, gross leak hermetic seal testing, particle impact noise detection testing, and acoustic microscopy.
Videos
- Package Inspection Techniques
- CSAM Video Presentation
- X-ray Microtomography Example
- X-ray Nanotomography Example
Failure Analysis - Procedures
Courses
- Gathering Information [+/-]
Gathering background information is a critical part of any failure analysis effort. Having the proper information and history on a failure can make an analysis run smoothly and avoid costly and time-consuming mistakes. This material covers the type of background information that should be gathered for an analysis.
- Principles and Procedures [+/-]
This material covers the principles and procedures that are used to guide the analyst through the failure analysis process. It includes topics on high level analysis flow, and specific topics like interpreting damage. This material also includes flowcharts on a variety of topics.
- Interpreting Overstress Damage
This section provides information to the analyst on how to interpret the difference between electrical overstress and electrostatic discharge as well as determine pulse width and amplitude.
- Principles and Procedures
This section covers some basic information regarding the evolution of failure analysis over the past 40 years. It also lists the basic philosophical and practical principles associated with failure analysis.
- Principles and Procedures - Part 2
This section covers the top level flowcharts associated with both packaged part failure analysis and wafer or die level yield analysis.
- Principles and Procedures - Part 3
This section covers the second level flowcharts associated with particular activities such as electrical characterization, package characterization, fault isolation at the chip level, defect localization at the gate/interconnect level, and materials characterization.
- Quiz: Principles and Procedures
This quiz reviews the basic concepts associated with the philosophy, practical rules, and procedures of failure analysis.
Documents
- Gathering Information [+/-]
- Principles and Procedures [+/-]
- Principles and Procedures
The principles and procedures of failure analysis are discussed, including product top-level analysis flowcharts, second-tier flowcharts, and analysis and technique orders.
Simulations
Chemistry Basics
Courses
- Chemistry Basics Overview [+/-]
This section covers basic chemistry principles that are the foundation for semiconductor processing. It also provides an important foundation for semiconductor packaging technology. Chemistry also plays a big role in failure analysis deprocessing techniques.
- Balancing Chemical Equations
This section covers the procedure for balancing chemical equations.
- Naming Compounds
- Limiting Reactants Experiment
This video shows an experiment that demonstrates how to determine the limiting reactant in a reaction.
- Balancing Chemical Equations Quiz
This quiz provides you an opportunity to see how well you have retained the concepts regarding balancing chemical equations.
Design is an important aspect of semiconductor technology. Without circuit designs, we would not have the functionality that currently exists in our computers, automotive electronics, telecommunications, military systems, and consumer electronics. Design requires an understanding of theory, transistor operation, and higher level abstractions of functionality. It also requires competence with the tools that create these circuits.
Courses
- Design [+/-]
This material covers general topics in IC design. IC design is a broad category. Right now, the system contains some basic presentations on design topics. It contains overview presentations on digital design, analog design, design validation, and other topics. This area will be expanded to include more topics and more detail in the future.
- Amplifiers and Multipliers
This section covers the basic design concepts behind CMOS amplifiers and multipliers. Topics covered include input stages, output circuits, feedback, and compensation.
- Analog Circuit Basics
This section covers basic analog circuit elements including the transistor, current source, the cascode connection, and voltage reference circuits.
- Design Validation
This section serves as a basic introduction to the concept of design validation. Design validation is becoming critical for today's complex ICs.
- Dynamic Analog Circuits
This section covers several dynamic analog circuits including sample and hold circuits, voltage offset reduction circuits, switched capacitor integrators, and dynamic comparators.
- Digital Fundamentals [+/-]
This course material covers fundamental concepts associated with digital circuit design. This section primarily concerns boolean algebra, logic notation, basic logic gates, truth tables, and methods for simplifying truth tables.
- Binary Number System
This presentation provides an introduction to the Binary Number System. The Binary Number System is the foundation of virtually all electronics data manipulation. It covers converting between the decimal and binary number systems, one's compliment arithmetic and two's compliment arithmetic.
- Basic Logic Gates
This section covers the basic logic gates including: the inverter, AND gate, OR gate, NAND gate, NOR gate, Exclusive-OR gate, and Exclusive-NOR gate. It also covers basic logic block construction.
- Basic Logic Operators and Boolean Algebra
This section covers basic logic operators and functions and boolean algebra.
- Logic Functions
This section describes how to create a logic function based on a truth table using a technique involving Karnaugh maps.
Failure Mechanisms [+/-]
Failures, although unwanted, are necessary to understand in detail in order to manufacture, package, and field semiconductor components and electronic systems. Failure mechanisms fall into four broad categories:
- Dielectric Failure Mechanisms
- Diffusion and Bulk Defects
- Interconnect Failure Mechanisms
- Package Level Failure Mechanisms
- Transistor Failure Mechanisms
- Use Condition Failure Mechanisms
This material describes a number of failure mechanisms in detail, providing a basis for the student understand how they occur, the physics that drive the mechanisms, their reliability impact (if any), and techniques or methods to mitigate them.
Courses
- Dielectric Failure Mechanisms [+/-]
This material covers dielectric failure mechanisms. This includes the dielectrics used for the transistor gates and the dielectrics used to isolate the interconnect. Dielectric breakdown is a common failure mechanism and has been studied for many years by scientists and engineers. This material represents the latest thinking on dielectric breakdown.
- TDDB - Introduction
This section provides an overview of the current state-of-the-art issues associated with oxide reliability. Specifically, the section covers the thin oxides used for gate dielectrics and tunnel dielectrics.
- TDDB - Oxide Breakdown Models
This section covers the most up-to-date thinking regarding oxide breakdown. The most current models based on voltage, electric field, carriers and the power law are covered.
- TDDB - Soft Breakdown
This presentation covers the relatively new phenomenon of soft breakdown. Soft breakdown does not immediately render the transistor non-functional, so one must understand the phenomenon in detail. It includes material on how to model soft breakdown events, and how to estimate time-to-failure.
- TDDB in Copper Low-K Systems
This section covers time-dependent dielectric breakdown in back-end dielectric materials. It includes material on models, copper migration, barrier layer, capping layer, and other effects.
- Time Dependent Dielectric Breakdown
Time-Dependent Dielectric Breakdown, or TDDB as it is also known, is a mechanism that degrades thin oxides subjected to high electric fields. A high electric field stresses an oxide, producing damage in the form of traps. These traps can eventually cause increased leakage. Sufficient leakage can result in dielectric breakdown.
- Time Dependent Dielectric Breakdown Quiz
This quiz covers the Time Dependent Dielectric Breakdown (TDDB) mechanism.
- Diffusion and Bulk Defects [+/-]
This material covers diffusion and bulk defects. Diffusion and bulk defects are defects that occur in the semiconductor material. They can be caused by contamination, improper processing, stress, and other events. Although these defects can result in yield loss and marginal operation, they rarely pose a reliability risk, because the temperatures required to cause their behavior to change is quite high.
This material is further broken down into diffusion alignment problems, diffusion profile anomalies, masking defects, under/over-sized mask features, and crystal defects. For more information, click on the topic of interest to view a short presentation on the subject.
- Diffusion Alignment Defects
This section covers diffusion alignment defects.
- Diffusion Profile Anomalies
This section covers diffusion profiles anomalies.
- Random Diffusion Masking Defects
This section covers random diffusion masking defects.
- Under or Oversized Masking Features
This section covers under/over-sized masking features.
- Interconnect Failure Mechanisms [+/-]
This material covers failures that occur in the IC interconnect system. Metallization failure is another topic that has been studied for many years by scientists. Metallization failures are common in integrated circuits and can occur because of stress or electromigration, as well as other mechanisms. This material represents the most current thinking regarding both electromigration, and stress voiding.
- Electromigration
This section discusses electromigration as it applies to aluminum interconnect and vias. We discuss the models and the effects of barrier layers, metal sandwich structures, and multiple contacts.
- Electromigration in Copper Low-k Systems
This section discusses electromigration as it applies to copper interconnect systems. We discuss the effects of liners, etch stop layers, CMP effects, copper alloying, and copper deposition conditions.
- Electromigration Quiz
This quiz covers the user's knowledge of electromigration.
- Stress Induced Voiding
This presentation covers the basic concept of stress induced voiding. We cover the physical mechanism and the main model used to understand this mechanism.
- Stress Induced Voiding - Case History
This presentation covers an example of stress voiding, how it was discovered and identified, and how it was eliminated from the process.
- Stress Induced Voiding in Current Technologies
This section covers stress migration/stress induced voiding in copper metallization systems. It addresses the effects of barrier layers, vias, grain size, alloying, and other issues specific to copper and low-k dielectrics.
- Stress Induced Voiding Quiz
This quiz tests the student's knowledge of Stress Induced Voiding.
- Package Level Failure Mechanisms [+/-]
This section covers reliability failure mechanisms in semiconductor components that are related to the package, or package and assembly process. It can be grouped into several categories: moisture and contamination, thermal degradation, and thermomechanical stress.
- Moisture and Corrosion
Moisture represents a significant threat to semiconductor reliability. A number of materials used in the semiconductor manufacturing and packaging processes can react with moisture (or moisture and an electric potential) and corrode. This section discusses this reliability mechanism.
- Thermal Degradation
Thermal degradation is a class of failure mechanisms that result in materials problems. At elevated temperatures some alloys can form that can have detrimental effects on the physical and/or electrical properties of a semiconductor component. Examples of this type of failure mechanism include intermetallic formation, or purple plague, and lead finish degradation.
- Thermomechanical Stress - Part 1
Thermomechanical stress is a group of failure mechanisms that are caused by the combination of mismatches in coefficients of thermal expansion between materials in the semiconductor component and thermal cycling or thermal excursions. These mechanisms include stresses to the bond wires, interactions between the die surface and the plastic encapsulating material, and stresses to the die itself.
- Thermomechanical Stress - Part 2
Thermomechanical stress is a group of failure mechanisms that are caused by the combination of mismatches in coefficients of thermal expansion between materials in the semiconductor component and thermal cycling or thermal excursions. These mechanisms include stresses to the bond wires, interactions between the die surface and the plastic encapsulating material, and stresses to the die itself.
- Transistor Failure Mechanisms [+/-]
This material covers reliability failure mechanisms in semiconductor components that are related to the transistor behavior. These mechanisms fall into several categories: hot carrier effects (HC), ionic contamination, and negative bias temperature instability (NBTI). Some mechanisms are well understood, like ionic contamination, while mechanims like NBTI are still poorly understood. This material represents the latest thinking on these mechanisms.
- High-K Gate Dielectric Reliability
This section discusses the reliability issues associated with the new high dielectric constant materials used for transistor gates.
- Hot Carrier Degradation
This section talks about the historical failure mechanism known as hot carrier degradation. It describes how it occurs, and the techniques used to mitigate its effects. Today, hot carrier effects are largely contained by scaling the voltage on the IC.
- Hot Carrier Degradation Quiz
This quiz covers hot carrier degradation.
- Ionic Contamination
This section talks about the historical failure mechanism known as ionic contamination. It is largely contained today by aggressively controlling cleanliness in the fab, removing human handling, and using ultra-pure chemicals. This section covers the major technological approaches for reducing ionic contamination is the circuit as well.
- Negative Bias Temperature Instability
This section covers Negative Bias Temperature Instability (NBTI), its effects on transistors and circuits, and how to characterize the mechanism
- NBTI Quiz
This quiz tests the student's knowledge of Negative Bias Temperature Instability.
- Use Condition Failure Mechanisms [+/-]
This section covers reliability failure mechanisms in semiconductor components that are related to use conditions or the environment. It can be grouped into two maincategories: electrical overstress/electrostatic discharge and radiation effects. Other overstress subjects like latchup and snapback are also covered in this material.
- Electrical Overstress and ESD
Overstress and ESD are common system-level problems that can affect semiconductor devices. There are four major overstress mechanisms: gross overstress, electrostatic discharge (ESD), latch-up, and snapback.
- Interpreting Overstress Damage
This section provides information to the analyst on how to interpret the difference between electrical overstress and electrostatic discharge as well as determine pulse width and amplitude.
- Radiation Effects
Radiation effects are a growing concern in many microelectronic devices. The most common radiation effect is the Single Event Upset or SEU. This can cause temporary errors in memories and logic path corruption in microprocessors. Another effect is charge build-up in oxides that can result in performance degradation.
Documents
- Failure Mechanisms [+/-]
- Electromigration
In this chapter we introduce the basics of electromigration, failure distributions, and ways to improve electromigration performance. Topics include: physical characteristics of metal films, mathematical models of electromigration, Blech effect, Blech length, Black's equation, and electromigration failure distributions.
- EOS/ESD
In this chapter we talk about electrical overstress and electrostatic discharge. Topics include: electrical overstress, electrostatic discharge, sources of ESD, reliability implications, mitigation techniques, latch-up, initiation, testing, mitigation techniques, and snapback.
- Hot Carrier Effects
Here we take a look at hot carrier injection mechanisms and the physical effects on circuits associated with them. Topics include: hot carrier injection mechanisms, effects on logic circuits, effects on memory circuits, deep submicron effects, negative bias temperature instability, mitigation techniques, deuterium anneal, and AC hot carrier effects.
- Ionic Contamination
This section discusses ionic contamination. It talks about the effects of contamination and the methods for controlling it.
- Moisture
In this chapter we talk about external package corrosion, inter-planar leakage, die-level moisture related mechanisms, and modeling moisture transport in plastic.
- Radiation Damage
Here we look at sources of radiation, the effects it can have, and ways to minimize those effects.
- Stress Induced Voiding
In this chapter we inspect the physics of stress induced voiding, including it's three main components: the driving force, nucleation point, and means to grow.
- Thermal Degradation
In this chapter on thermal degradation, we look at intermetallic formation and the thermal degradation of lead finish.
- Thermomechanical Stress
Covered in this chapter are several failure mechanisms, including die cracking in ceramic packages, die cracking in plastic packages, plastic package cracking and popcorning, bond wire damage, thin film cracking, and accelerating thermomechanical stress.
- Time Dependent Dielectric Breakdown
Here we examine several aspects of breakdown, including Fowler-Nordeim tunneling, direct tunneling, trap assisted tunneling, bandgap ionization model, classic anode hole injection model, hydrogen release model, thermochemical model, accelerated stress testing, voltage ramp, current ramp test, AC effects, and extrinsic breakdown.
Videos
MIL-STD Training
Courses
- Pre-Cap Visual Inspection [+/-]
- Introduction and Overview
This presentation describes Pre-Cap Visual Inspection and its application to high reliability components. It discusses the history, documentation, advantages, and disadvantages of the methodology.
- Equipment for Pre-Cap Inspection
This presentation describes the equipment used for Pre-Cap Visual Inspection. This includes optical microscopy, camera technology, and ESD workspaces.
Packaging Design [+/-]
This material covers the electrical behavior, thermal properties, and the structural and mechanical aspects of electronic packaging. As packaging technology increases in complexity, a whole host of electrical, thermal, and mechanical issues must be accounted for and modeled. The electrical issues include resistance, capacitance, cross talk issues, power and ground bus disturbances, and high frequency packaging. Thermal issues include heat dissipation, the uses of ceramic and plastic, actively cooled packages, heat sinks and planes, and materials issues. Mechanical include thermal coefficient of expansion issues, plastic vs. ceramic packaging, as well as soldering issues. This material also covers the modeling techniques used to characterize these issues.
Courses
- Courses [+/-]
- Course and Instructor Overview
This presentation provides an overview of the Packaging Design and Modeling Course and an gives some background information on our Packaging Design expert, Steve Groothuis.
- Packaging Engineering and the Electronics Ecosystem
This presentation describes the function of Packaging Engineering and discusses the various disciplines involved in packaging, including mechanical engineering, materials engineering, electrical engineering, and industrial engineering. It also discusses the role of Packaging Engineering in the broader context of the electronics ecosystem.
- The ITRS and Its Impact on Packaging Design and Modeling
This presentation describes the International Technology Roadmap for Semiconductors (ITRS) and discusses the portions of the roadmap that apply to packaging design, modeling and simulation.
- JEDEC Packaging Standards
This presentation describes the Joint Electron Device Engineering Council (JEDEC) and the industry standards related to packaging design and the various package configurations.
Videos
- Videos [+/-]
- Ceramic Dual Inline Package Animation
This brief animation shows a ceramic dual inline package from different angles with and without the lid.
- Chip Scale Package
- Lead-On Chip Package Animation
This brief animation shows the lead-on-chip package animation from different angles with and without the lead frame exposed.
- MicroBGA: Lead Frame Preparation
This animation describes the lead frame preparation process for a micro Ball Grid Array (BGA) package.
- MicroBGA: MF-LOC
This animation describes the assembly process for a multiframe lead-over-chip (MF-LOC) package.
- MicroBGA: QFN
This animation describes the assembly process for a Quad Flat No-Lead (QFN) device.
- MicroBGA: Solder Bump Formation
This short animation describes the solder bump formation process for a Micro Ball Grid Array (BGA) package.
- MicroBGA: Terminal Formation
This short animation describes how terminals are formed for MicroBall Grid Array (BGA) and Quad Flat No-Lead (QFN) packages.
- Plastic Dual Inline Package Animation
This brief animation shows a plastic dual inline package with and without the die exposed.
- Solder Bump Animation
This brief animation describes two methods for forming solder bumps using micropunching technology, the direct method, and the plate transfer method.
Packaging Technology [+/-]
Semiconductor packaging is becoming increasingly challenging. As integrated circuits increase in performance, new packaging techniques are required to remove the heat, handle the increased number of bondpads, and deal with the fragile Lo-K dielectrics used on these circuits. New technologies such as optoelectronics and microelectromechanical systems (MEMS) can require specialized packages. Smaller form factors require engineers to use higher density packaging options, like array packaging, chip scale packaging, and multi-chip modules. Although packaging can be a challenge, it can also provide a lower cost path for integration needs. For example, a system in a package design can be more cost effective than a system on a chip design. This section covers packaging technology issues, packaging design and modeling issues, as well as packaging reliability challenges.
Courses
- Business Trends and Drivers [+/-]
This section covers the business environment and the technical drivers that affect semiconductor packaging. The relentless pursuit of Moore Law by the semiconductor industry, the proliferation of packaging formats, and the introduction of new materials, have made packaging technology challenging in recent years. This section also provides an overview of these issues, and other issues, such as the rise of the system in a package (SIP) approach.
- Business Trends and Drivers
This section covers the semiconductor industry trends and drivers that affect the packaging community. We discuss the impact of Moore's Law, consumer electronics and its requirement for low cost, low power, and small package footprints.
- ITRS Roadmap
This section describes the packaging issues and needs that arise from the requipmenets of the International Technology Roadmap for Semiconductors (ITRS).
- Lead Free Issues [+/-]
Lead-free electronics is fast becoming a reality. The pressure from the European Union, Japanese, and other legislative bodies almost guarantees that the industry will completely convert in the next several years. Right now, many manufacturers are using their lead-free components as a differentiator in the marketplace. The key challenges to going lead-free are technical and logistical in nature. On the technical side, the new solder alloys must be characterized for reliability performance. The surrounding materials must be able to withstand the higher reflow temperatures as well. On the logistics side, the conversion coordination will require a good deal of effort, since this involves schedules, supply lines, manufacturing processes, and other items. This section covers these issues in further detail.
- Lead Free Issues
Because of governmental directives, the electronics industry is moving away from lead-based solders to lead-free solders. Although lead-free solders can work to connect components to printed circuit boards, there are some issues. Lead-free solders have different properties than leaded solders, requiring different reflow temperatures, different flux materials, and new reliability characterizations. This section discusses these issues in more detail.
- System-on-a-Chip vs. System-in-a-Package [+/-]
This material covers issues related to System on a Chip (SoC) and System in a Package (SiP). Both technologies have their advantages and disadvantages.
- Use Conditions [+/-]
As the complexity of electronics increases, it is becoming more difficult to use a one size fits all approach to reliability and qualification. Instead, most manufacturers now use a market segmentation approach that takes into account the use conditions of a component. Different environments require different levels of reliability. Those same environments can affect reliability strongly. The approach used for reliability and packaging qualification is referred to as the knowledge-based reliability approach. This section covers this concept in more detail.
- Low-K Issues [+/-]
This material covers low dielectric constant materials issues associated with the packaging process. Low-K materials are soft and have poor mechanical properties. This requires special approaches so that the packaging process does not damage these materials. Low-K materials also require special test techniques to monitor the affect of the packaging process on them.
- Low-K Issues
This section describes the problems related to packaging an IC that uses low-k dielectrics. It also describes several characterization methods for determining if a low-k dielectric will withstand the packaging process and the environment associated with its use conditions.
- Copper Low-k Impact on Package Reliability
This section discusses a number of reliability failure mechanisms associated with interactions between the packaging process and the copper and low dielectric constant materials. It covers oxidation, corrosion, thermal cycling, wire pull and wire shear tests, and package stress.
- Polymers [+/-]
- Mechanical Behavior of Solids
This section covers the mechanical behavior of polymers. This includes properties like glass transition temperature, the coefficient of thermal expansion, fracture toughness, elastic modulus, viscoelastic behavior, adhesion, peel strength, and water absorption.
- Polymer Case Studies
This section covers three case studies involving problems with polymers in electronics applications. They include a coefficient of thermal expansion problem with a connector between a board and a daughtercard, degradation of a thermal interface material that holds a cooling pipe network in a package, and a delamination problem associated with water uptake in a polymer.
- Specialty Polymers in Electronics
This section covers polymers that are used in semiconductor packaging applications. They include polyimides and liquid crystalline polymers. The chemical composition, shape, and properties are discussed.
Photovoltaics
Courses
- Photovoltaics Overview [+/-]
Photovoltaics, or solar cell technology, is a rapidly growing segment within the world economy. Many companies and organizations are pursuing a variety of solar cell technologies to create cost-effective, efficient electricity from the sun. Solar cell technologies fall into two main groups (thin film and bulk technologies). Within each group, engineers and scientists are pursuing both silicon and compound semiconductor materials. Some groups are even pursuing organic materials. Currently, our website covers silicon photovoltaics materials. We are also developing additional content that will cover compound semiconductor photovoltaic materials. The material covers both the technology and manufacturing of photovoltaics. It helps to illustrate the tradeoffs between cost and performance for this alternative energy source.
- Outline
This brief section provides an overview of the topics covered in the following presentations.
- Introduction to Silicon Photovoltaics Technology
This section introduces photovoltaics as an energy source and explains why there is growing interest in the technology. It also discusses greenhouse gases and how solar energy can reduce the growth of greenhouse gases.
- Properties of Sunlight
This section covers the properties of sunlight including the relationship between wavelength and energy, direct and diffuse sunlight, the standardized solar spectra, solar irradiance as a function of wavelength taking into account atmospheric effects, and insolation around the world.
- Semiconductor Properties
This section covers the semiconductor properties that specifically pertain to solar cells. This includes crystal structure, doping, generation, light absorption in silicon as a function of temperature, wavelength and thickness. It also covers recombination, diffusion and drift as well as the basic p-n junction and pn diode equation.
- Solar Cell Structure
This section describes the solar cell structure in terms of optimizing electron-hole pair generation and collection. It covers diffusion length effects, surface passivation and recombination, quantum efficiency, IQE, the photovoltaic effect and the current-voltage characteristics. It also discusses the effects of loading and series resistances and dark current light intensity effects, and temperature effects.
- Design of Silicon Cells
This section covers the basic design principles involved in creating an efficient silicon photovoltaic cell. It covers anti-reflection coatings, surface texturing, recombination, back surface fields, resistance effects in the silicon, contacts, as well as the interconnect. There is also a discussion of compromises that need to be considered when designing a cell panel.
- Manufacturing Cells
This section covers the manufacturing steps involved in creating a silicon solar cell. It covers silicon crystal growth, wafer or panel slicing, diffusion of dopants, the screen printing process, buried contact technology, and configurations such as PERL and emitter wrap-through cells.
- Solar Cell Production Line
This section describes the factory process steps associated with the manufacture of the silicon photovoltaic cells. It includes the growth process, wafer sawing systems, texturing, the diffusion and isolation processes, the anti-reflection coating process, the screen printing process, the firing process, and final test and sort.
Processing
Courses
- Lithography [+/-]
Lithography is a key component of IC manufacturing. It is also one of the most expensive steps in the IC manufacturing process. Today's ICs go through the lithography step some 20 to 30 times to pattern the isolation layers, transistors, gates, and interconnect. Lithography is also used in the packaging process as well. This material covers the physics of lithography, resolution, the photoresists used in lithography, and lithography techniques.
- Lithography - Introduction
This section provides an overview of lithography. It describes basic concepts such as optics, resist, and printing.
- Lithography - Resolution
This section discusses resolution as it applies to lithography. It covers properties of light, diffraction, phase shift masking, and optical proximity correction.
- Lithography - Resists
This section covers both positive and negative resists for lithography. It also covers hard mask technology.
- Lithography - Future
This section covers the future of lithography. It includes discussions on EUVL, SCALPEL, X-ray lithography, nano-imprint lithography, and immersion lithography.
- Materials for Processing [+/-]
This course covers the materials that are used in semiconductor processing. The main focus of this material is on low-k materials, but will be expanded to include chemicals and gases.
- Low-K Materials
This section describes a number of low-k materials that are being considered for semiconductor manufacturing.
- Etch Stop Materials for Low-K Dielectrics
This section discusses etch stop materials and hard masks that are used in conjunction with low dielectric constant materials in semiconductor processing.
- Process Integration [+/-]
This section also covers the art and science of combining the unit processes into an overall process for fabricating an integrated circuit, called process integration. Process Integration is highly governed by the interactions between individual processes. One process can affect the results of a previous process, or even preclude the use of a process elsewhere. In this section, we cover process modules, and the overall process for CMOS, Bipolar, BiCMOS, and Power Semiconductor Devices.
- LOCOS and STI
This section provides an overview of the basic process integration steps associated with transistor isolation. Specifically, we discuss LOCal Oxidation of Silicon (LOCOS) and Shallow Trench Isolation (STI).
- Salicide and BEOL
This section provides an overview of the salicide process and the contact formation process.
- Process Integration Quiz
This quiz tests the student's general knowledge of CMOS and BiCMOS Process Integration. The quiz includes questions on device physics, basic processing, materials, reliability and yield.
- Unit Processes [+/-]
This material covers the unit processes involved in semiconductor manufacturing. It includes processes such as diffusion, implantation, etching, chemical mechanical planarization, chemical vapor deposition, and others. Unit processes are combined with cleaning and inspection steps to create a process module. These process modules are then linked together to create a process flow for manufacturing the device. Each unit process in today's ICs is quite complex, requiring expensive equipment and in-depth knowledge of chemistry, physics, and related disciplines.
- Cleaning Methods
This section covers cleaning methods for semiconductor wafers. We discuss ultrasonic, megasonic, cryo-cleaning, aerosol cleaning, and chemical cleaning processes.
- Chemical Mechanical Planarization
This section covers chemical mechanical planarization (CMP). We discuss the tools, methods, and materials used for CMP.
- Deposition
This section covers physical vapor deposition and chemical vapor deposition techniques.
- Diffusion
This section covers the diffusion process. We discuss the physics of diffusion, dopant species, electrical, and concentration effects.
- Ion Implantation
This section covers ion implantation. We discuss the physics of ion implantation, ion implantation methods, dopant species, damage effects and annealing.
- Oxidation
This section covers wet and dry oxidation. We cover oxidation models as well as concentration effects.
- Starting Material
This section covers the basics of silicon crystal structure, defects, the growth process, sawing, and wafer identification.
- Wet and Dry Etching Processes
This section covers wet chemical and reactive ion etch processes for removing materials from a semiconductor device.
Documents
- Unit Processes [+/-]
- Chemical Mechanical Polishing
Various aspects of CMP are discussed, including CMP variables and physics, Oxide CMP, Tungsten CMP, Copper CMP.
- Deposition
The deposition topics covered here include silicon epitaxial growth, physical vapor deposition, sputtering, molecular beam epitaxy, chemical vapor deposition (CVD), spin-on dielectrics, and electroplating.
- Starting Material
Several topics dealing with starting material (silicon) are discussed in this chapter. Some of them include the manufacture of single crystal silicon, incorporation of impurities, float zone process, wafer sawing and wafer dicing operations, silicon on insulator, and silicon crystal defects.
- Wafer Cleaning
Several wafer cleaning methods are explored in this chapter, including particulate removal, film removal, RCA cleaning, pihrana cleaning, alternate cleaning, and rinsing and drying.
Videos
- Process Integration [+/-]
- Unit Processes
- Ion Implantation Animation
- The Zincblende Lattice
Reliability Overview [+/-]
Reliability is defined as the intrinsic "goodness" of a component, and implies that a component will work according to its specification for some defined period of time. In order to understand reliability, one must have a basic understanding of the following items:
- Reliability Terms and Definitions
- Statistics and Distributions
- Failure Mechanisms (die level, package level, system level, and use conditions)
- Test equipment
- Test structures
- Accelerated testing techniques
This material covers these six topics in detail, including reliability terms, statistics and distributions, calculating reliability, test equipment and structures, and the methods for determining the operational (and non-operational) lifetime of a microsystem. It also covers the physics and the methods used for determining the various mechanisms that can cause performance degradation.
Courses
- Introduction to Reliability [+/-]
Reliability is an important aspect of semiconductor design and manufacturing. Customers expect devices to work correctly through the expected life of the component. In some applications like medical implants, defense, and space, the consequence of failure is enormous. This requires extra attention to reliability. This material introduces the subject of reliability to the engineer/scientist.
Documents
- Introduction to Reliability [+/-]
- Quality and Reliability
Here we talk in general about quality (process variation and control), reliability, failure mechanisms (ESD, stress voiding, etc), and yield.
Reliability Statistics [+/-]
Reliability is a discipline driven by data. In order to predict the reliability of a component, one must use test data to predict the response of the component or electronic system. This requires an in-depth understanding of statistics and distributions. This material covers basic statistics and distributions used for reliability calculations, how to handle situations where no failures occur, how to transform data from test structures to use conditions, and how to calculate system level reliability based on individual reliability numbers from components or failure mechanisms.
Courses
- Reliability Statistics [+/-]
One important aspect of reliability engineering is statistics. The reliability engineer should have a good grasp of statistics and distributions. All reliability-related failure mechanisms can be mapped to a particular distribution type. The most common distributions used in reliability studies are the exponential distribution, the normal distribution, the lognormal distribution, and the Weibull distribution.
- Statistics and Distributions
- Statistics and Distributions Quiz
- Which Distribution Should I Use?
- Distribution Graphing Problems
- Lognormal Distribution Example
- Probability of Lot Acceptance
- Calculating Component/System Level Reliability
Documents
- Reliability Statistics [+/-]
- Reliability Graphing Paper
This file contains Lognormal, Weibull, and Semi-Log (Exponential) graphing paper.
- Standard Normal CDF Table
This table contains calculated Standard Normal CDF values. These are used for calculating system reliability numbers when lognormal distributions are involved.
Reliability Testing [+/-]
In order to make an accurate prediction concerning the reliability of a component or system, one must have data on the behavior of the system, or its individual components or failure mechanisms. While these can be estimated based on other experiments or data, it is best to gather data from the system, components, or surrogate test structures directly. This material describes test structures, test equipment, and the type of tests that are performed to generate reliability data. It includes material on burn-in, humidity testing, thermal cycling, and other types of accelerated testing.
Courses
- Reliability Testing [+/-]
Testing is a key aspect of reliability evaluations. Testing must be performed not only for individual failure mechanisms, but also at the component level. Component level testing helps ensure that all potential failure mechanisms are addressed. There are two types of testing at the component level: electrical screens and stress/life tests. Electrical screens are performed using automated test systems and are similar to standard functional tests. Stress and life tests are performed over longer periods of time under accelerated conditions. These conditions could be higher voltage levels, higher temperatures, high humidity levels, or a combination of each.
- Developing Electrical Screens
This section covers electrical and parametric screens that are performed to aid in the reliability evaluation of an IC.
- Developing Stress Tests and Life Tests
This section covers burn-in, life tests, HAST testing, and other humidity testing used to evaluate the reliability of packaged ICs.
- Reliability Test Equipment [+/-]
Reliability test equipment is an important consideration for accelerated testing. Reliability testing is performed at the wafer level and at the packaging level. In order to provide more timely feedback, manufacturers prefer to use wafer level testing. This section discusses equipment for both wafer level and packaged part level. We also cover probe technology for wafer level probing.
- Reliability Test Equipment - Wafer Level
This section covers wafer level reliability test equipment. It includes material on probers, source measurement units, switch matrices, and software.
- Reliability Test Equipment - Probes
This section covers probe card and probe tip technology for wafer level probing.
- Reliability Test Equipment - Packaged Parts
This section covers reliability test equipment that is designed for testing packaged ICs. It includes discussions on burn-in equipment, humidity testing, and other reliability-related testing.
- Reliability Test Structures [+/-]
Testing at the wafer level requires appropriate electrical elements on the wafer. These electrical structures must simulate and magnify problems that normally occur on finished components. This section discusses test structures and their use in reliability testing.
- Test Structures - Basics
This section covers basic test structures and their use for reliability characterization. It also includes basic information on the purpose of test structures.
- Reliability Test Structures
This section covers test structures that are designed specifically for reliability characterization. This section describes TDDB-specific structures and how they can be designed to help separate and identify different effects.
- Self Stressing Test Structures
This section covers self-stressing test structures and their use in more accurately characterizing reliability degradation mechanisms.
Documents
- Reliability Testing [+/-]
- Screens, Stress Tests, and Life Tests
Overview of screens and various tests. Topics include: ATE based screens, IDDQ, statistical process control, burn-in, life tests, highly accelerated stress test, acceleration factors and distributions, equipment, times, temperature, and biasing.
- Reliability Test Equipment [+/-]
- Reliability Test Structures [+/-]
Technology [+/-]
Semiconductor Technology encompasses the fundamental device groups and the methods used to create these technologies. This encompasses Logic Devices (Digital), Analog Devices, Mixed Signal Devices (Analog and Digital on the same chip), Memory Devices, High Voltage Devices, High Frequency Devices, Optoelectronics, and Micro Electro Mechanical Systems (MEMS). There are a number of key processes that enable these devices that include CMOS (Complimentary Metal Oxide Semiconductor), Bipolar, MESFET (Metal Electrode Semiconductor Field Effect Transistors, and a wide range of lesser processes.
Courses
- Interconnect Technology [+/-]
Today's ICs may contain kilometers of interconnect and billions of vias, so the interconnect system must be manufactured with the utmost precision. This course covers issues associated with interconnect on semiconductor devices. It covers both aluminum and copper interconnect systems.
- Memory Technology [+/-]
This material covers the technology of memory ICs. Memory is ubiquitous in today's electronic systems. There are several types of memory: dynamic random access memory (DRAM), static random access memory (SRAM), and non-volatile memory (NVM). Each has its advantages and disadvantages, and each has different design and manufacturing techniques.
- Memory Technology Overview
This section provides an overview of memory technology. It covers Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Non-Volatile Memories like NAND and NOR flash. It also covers a history of the basic non-volatile memory technologies, including NMOS, SONOS, FLOTOX, and flash memory.
Videos
- Memory Technology [+/-]
- Energy Band Transitions
This animation covers the basic energy band transitions that can occur, including: interband transitions, intraband transitions, and assisted transitions.
- pn Junction Diodes
This interactive graph demonstrates the current voltage characteristics of a pn junction or diode. We plan to add more details to the operation of this graph in the near future.
This workspace covers semiconductor and integrated circuit test. Test is a critical aspect of the design and manufacturing process. Test allows one to determine if the device is working correctly, and it can also give insight into potential failure mechanisms and manufacturing issues. In this section we cover: defect modeling, design for test, digital testing, analog testing, parametric testing, and test hardware.
Courses
- Defect Based Testing [+/-]
Defect-based testing is the practice of testing with the idea of detecting defective conditions on complex ICs. Defect-based testing moves beyond functional and structural testing by introducing test concepts to catch actual defects. Many defects are not easily caught with standard test techniques, and require additional test approaches. Defect-based testing incorporates knowledge of defects like opens, shorts, resistive connections, parametric anomalies, and process variation-induced problems. It requires an understanding of the electrical behavior of these defects. The electrical behavior can be turned into a defect model, which in turn leads to effective test approaches like at-speed testing, delay testing, IDDQ testing and low voltage testing. These are test strategies that are used in conjunction with standard functional and structural test. These test approaches also require an understanding of automatic test pattern generation (ATPG), since one must generate vector sets to catch these problems. Defect-based testing also is critical for failure analysis troubleshooting activities. Defect diagnosis uses these concepts and test techniques to help automatically detect defects.
- Introduction to Defect-Oriented Testing
This section provides an overview to defect-based testing. It explains how defect-based testing differs from standard test techniques and why it should be performed.
- ATPG Basics
This section introduces the concept of Automatic Test Pattern Generation. It covers pseudorandom and deterministic patterns. It also covers ATPG program flow and the search problem associated with ATPG.
- ATPG Algorithms
This section covers the mathematical basis of automatic test pattern generation routines. It includes information on the D-Algorithm, Branch and Bound techniques and heuristics.
- CMOS Defect Mechanisms and Detection Overview
CMOS ICs exhibit particular responses to defects. Defects such as particles, mask defects, and etching problems can cause the IC to malfunction. This section covers the basic defects found on ICs and discusses their implications on the operation of the IC.
- CMOS Opens and Detection Techniques
Open circuits exhibit particular behaviors in CMOS ICs. They can range from stuck-at behavior to more complex, time-varying behavior depending on the location of the open, the topology of the circuit and the circuit design itself. This section covers the behavior of open circuit defects, the methods used to detect these opens, and discusses the basic fault models associated with them.
- CMOS Shorts and Detection Techniques
Short circuits exhibit particular behaviors in CMOS ICs. While most shorts will elevate current, the functional behavior can be more complex to understand. This section covers shorts, how to model them, and how to best detect them with both current and voltage-based techniques.
- Defect Classes
This section covers defect classes and the electrical behavior of these defect classes. We concentrate on the bridging defect class, the delay defect class, and the open defect classes.
- Detection Techniques for CMOS Defects
This section briefly covers the voltage and current techniques used to detect defects. It also discusses the nature of defects on test and reliability.
- Failure Mechanisms in CMOS IC Materials
This section covers some basic information about failure mechanisms. We concentrate on CMOS defects, since CMOS is the most complex technology from a test standpoint. We also briefly discuss issues associated with process variations.
- Parametric Defects and Detection Techniques
Parametric defects are becoming more common as chip designs move into the nanometer scale. Slight variations in the process lead to parametric defects that fall just outside of the intended operational range of the IC. There may be no defects present, but the circuit doesn't work as intended. Parametric defects require special test strategies, and a coordination between design and manufacturing. We discuss this issue in more detail in this section.
- Test Basics [+/-]
This material covers basic issues in test. Currently, this course contains an introduction to automatic test and an overview of boundary scan test techniques.
- Automatic Testing Overview
This section introduces the concept of automatic testing of integrated circuits. It provides an overview of why testing is performed, and the equipment used to test ICs.
- Boundary Scan Overview
This section introduces the boundary scan standard (IEEE 1149.1). It explains the use of boundary scan and discusses the ports, the test access protocol and the basic state diagram for the controller.
- Test Methodologies [+/-]
This course material covers test methodologies for ICs. It includes information on digital testing, current testing, and timing tests. All three are useful to help localize defects and other problems on circuits prior to shipping them to the customer.
- Test Process Basics
Test process basics provides an overview of the test process and how defect-based test fits into it. This section covers the development of the test set from design through to production and the various components of test. It also discusses approaches such as random test pattern generation, and scan-based approaches for combinational and sequential circuits.
- IDDx Testing
Quiescent Power Supply Current, or IDDQ testing is an important component of a test strategy for a complex IC. IDDQ, differential IDD, an time-based IDDQ measurements form the body of IDDx testing techniques. This section covers IDDx techniques in detail. It also includes discussion of techniques to use IDDQ with higher current ICs, a big issue because of today's thinner gate dielectrics and small feature sizes.
- Low Voltage Test
Low voltage test is a less common test technique, but it has been shown to help detect some types of defects. Low voltage test operates on the principle that defect currents scale differently than transistor drives currents when the voltage is lowered. This can bring out potential defective conditions. This section covers this concept in more detail.
- Timing Tests in Production
The most common, and most difficult, parametric defects to detect are timing problems. Timing problems require strategies such as varying the frequency of the IC under test, and changing the clocking signals in the scan circuitry. We discuss these techniques in more detail in this section.
- Fault Models [+/-]
This course material covers fault models that are used by engineers to develop test routines for complex chips. A fault model is an abstract concept designed to translate the behavior of a defect into a condition that can be tested, preferably on a digital test system.
- Fault Models for Defect-Based Test
This section introduces the concept of fault models, why they're needed, and for what purpose they're used. The section covers the four basic uses of fault models: test generation, fault simulation, quality prediction and fault diagnosis.
- Bridging Fault Models
This section covers Bridging Fault Models and how to deal with various types of bridging possibilities in a circuit.
- Delay Fault Models
Many defects in advanced CMOS ICs can be modeled with the delay fault model. Implementing the delay fault model can be quite challenging in a complex circuit. To that end, researchers have developed several approaches to both model delay faults and simplify the process of implementing tests for delay faults. These models include the transistion fault model, and the gate delay, path delay, line delay, and segment delay fault models.
- Fault Diagnosis Algorithms
Fault Diagnosis Algorithms are the basis of Automatic Test Pattern Generation. Because of circuit complexity, computer-generated patterns are preferred over manual pattern generation. Algorithms operate on the chip design information using models such as the stuck-at fault model to create a test pattern. Algorithms discussed in this section include the D-algorithm, PODEM, FAN, pseudo-random algorithms, weighted algorithms, and more.
- Fault Dictionaries
Fault Dictionaries are an alternate means to retain information about electrical faults on ICs. A Fault Dictionary is a database of some or all of the faults that can occur in an IC. The dictionary can then be used in conjunction with a test program or strategy to localize the problem on the circuit. In a complex IC, this dictionary can be quite large, so various strategies are used to compress the it, or divide it into sections using boundary scan. This section covers Fault Dictionaries and related techniques in more detail.
- Stuck-At-Fault Testing
This section briefly describes the stuck-at fault model and how it works. It also provides a simple example and a discussion on how to create a computer algorithm based on the concept.
This material covers the topic of Yield Analysis and Modeling. Yield is a critical aspect of the semiconductor manufacturing process. High yielding components are necessary for profits and success at Foundries as well as the Integrated Device Manufacturers. This material covers the Principles and Procedures of Yield Analysis, Yield Analysis Techniques, Yield Modeling, Data Mining, and Yield Enhancement Techniques.
Courses
- Models [+/-]
- Introduction to Yield Analysis
This section provides an overview of yield analysis. The terminology, goals, and approaches to yield analysis are introduced. We also give several examples of some basic yield analysis problems, how they were addressed, and how they were resolved.
- Advanced Yield Modeling
Advanced Yield Modeling covers yield modeling techniques that provide additional granularity in the overall yield of a product. This body of knowledge is sometimes call integrated yield management. Comparing parameters using a scatterplot can be challenging. Data interpretation can be quite difficult. The idea behind integrated yield management is to tie processing parameters to yield by reducing the data to a more simplified format, making graph interpretation straightforward.
- Basic Yield Models
This section covers basic models used to predict the yield for a die given a particular size and defect density. This includes models like the Price Model, Seeds Model, Bose-Einstein Model, Murphy Model and others. We discuss the advantages and disadvantages of each.
- Critical Area Analysis
This section covers methods to predict where defects might adversely affect the operation of a chip, resulting in yield loss. These methods provide a more accurate estimation of yield, but require extensive computer processing on the layout information to derive this more accurate number.
- Data Mining Statistics and Plotting
This section covers covers basic statistics used in yield analysis scenarios. We cover how one turns generic data into histogram format, the normal distribution and lognormal distribution, and we discuss the chi-square goodness of fit for data. We also discuss various methods for displaying data, including normal plots, lognormal plots, scatter plots, and box plots.
- Defect Analysis and Yield Loss
This section covers defects and their impact on functionality. Normally, defect analysis includes determining the probability that the defect will occur, and the probability that it will cause a failure in chip operation. The former probability is usually referred to as the defect density, and the later probability is usually referred to as the kill ratio. We explain how to determine which problems should be addressed first based on kill ratios and defect densities.
- Procedures [+/-]
This course material covers the procedures associated with Yield Analysis. We cover procedures and methods that are used to help improve yield. These can be techniques used at the design level as well as techniques to address yield problems that are currently occurring.
- Yield Analysis Principles and Procedures
This section covers the high level principles used in yield analysis. We also spend time discussing the procedures from a general perspective. This includes the general approach, data-gathering phase, fault localization, electrical characterization, and analytical characterization activities.
- Yield Enhancement Techniques - Proactive
This section covers proactive steps to improving yield. We cover design techniques that are used in the industry to reduce the probability of defects causing problems in the layout. We also cover design techniques that reduce sensitivity to process variations, and sub-wavelength lithography issues.
- Yield Enhancement Techniques - Reactive
This section covers reactive steps to help restore or improve the yield of an existing line. We cover triage approaches, as well as techniques for identifying random defects and systematic defects. We also cover yield ramp up activities and product monitors. Last, we cover kill ratios and how to use the information to address yield problems.
- Yield Methods for Low Volume Manufacturing
Yield improvement is a challenging activity in a low volume manufacturing environment. The ability to run experiments on wafer lots and gather data is limited. Furthermore, the data is limited to make judgments on yield changes. The best approach is to study the wafer lots one does have in as much detail as possible, and generate as much data as possible for each wafer lot. We discuss these approaches, as well as increased use of test structures and product monitors.
- Root Cause Analysis
This section covers the techniques used to identify the root cause of failure. This section includes definitions, general principles, the basic procedure, and information on a number of specific root cause analysis techniques. We include information on 5 Whys, FMEA, Fault Tree Analysis, Fishbone Diagrams, Cause Mapping, Apollo Root Cause Analysis, and more.
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