2006 December Newsletter

Volume 2, Issue 11

December 2006

Welcome to the Semitracks Online Monthly Newsletter! It is our goal that you find this newsletter interesting, informative and useful. Please email any comments or feedback to This email address is being protected from spambots. You need JavaScript enabled to view it. .


1. News

Upcoming Course - Wafer Fab Processing

This new intensive 4-day course offers a comprehensive examination of the wafer fab processes used to manufacture state-of-the-art microchips. Topics include semiconductor devices and ICs, silicon crystal growth and crystal defects, ion implantation, thermal processing, contamination control, wafer cleaning, LPCVD, PECVD, PVD, CMP, microlithography, etch, multilevel interconnect technology, and manufacturing technology. Process integration will be illustrated using a basic CMOS process flow.

The course is designed primarily for process engineers and process technicians. The emphasis is on understanding how each individual process step works, and understanding the key process control variables for each step. The functional design of the process tools is also discussed, as are process characterization, monitoring, and control.

Engineers new to semiconductor manufacturing will gain a solid, broad understanding of the entire wafer fab process. Engineers experienced in one or more functional areas of wafer fab will benefit from a thorough understanding of processes in other areas, as well as a better appreciation of process interactions.

Each student will also receive a copy of Microchip Manufacturing by Stan Wolf. This unique, full color book is a "must have" reference text for anyone working in the semiconductor industry.

Semiconductor Processing

  • (February 26-March 1, 2007) - Santa Clara, California

2. Course Schedule

Invest in yourself and your staff. Our 2007 schedule is now available, come and learn from the experts!

CMOS and BiCMOS Process Integration

Semitracks, along with Semiconductor International, have put together a three-day course on Semiconductor Process Integration for CMOS and BiCMOS Technologies. Dr. Badih El-Kareh, an independent consultant, will give an overview of the process integration challenges associated with today's advanced semiconductor devices. Dr. El-Kareh will cover passive and active components, contact and interconnect issues, isolation technologies such as STI and SOI, transistor integration issues, as well as full CMOS, BiCMOS and high speed bipolar process integration techniques. To learn more, click on the link below to visit the course page.

Process Integration

  • (January 29-31, 2007) - Tempe, Arizona

Failure and Yield Analysis Course

Failure and Yield Analysis is an increasingly difficult and complex process; engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. This is a multi-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure.

Failure and Yield Analysis

  • (March 12-15, 2007) - Santa Clara, California

Semiconductor Reliability

Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. Analysis and experimentation is now performed at the wafer level instead of the packaging level. This requires knowledge of subjects like: design of experiments, testing, technology, processing, materials science, chemistry, and customer expectations. While reliability levels are at an all-time high level in the industry, rapid changes may quickly cause reliability to deteriorate. Your industry needs competent engineers and scientists to help solve these problems.

Semiconductor Reliability

  • (March 27-29, 2007) - Santa Clara, California

Packaging Technology and Challenges

Semitracks, Inc. and Semiconductor International have put together a course which will provide an overview of the current business climate, anticipated trends and the associated impact on assembly/packaging roadmaps. There will be an in depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution.

Packaging Technology and Challenges

  • (April 9-10, 2007) - Tempe, Arizona

Packaging Design and Modeling

Semitracks, Inc. and Semiconductor International have assembled a course on IC Packaging Design and Modeling. This course provides an overview of the packaging design process. The course covers current packaging technologies, including chip scale packaging, Ball Grid Array technology and other current concepts. This class focuses on techniques and the importance of thermal and mechanical simulations. Discussions and examples will concentrate on thermal performance simulations, assembly & packaging stresses, package reliability (including solder joint fatigue simulation), and interactions between chip and package. In addition, a special section will be examples of successful wafer level simulations.

Packaging Design and Modeling

  • (April 11-13, 2007) - Tempe, Arizona

To register for our courses, register online or download the registration form. You can fax the completed form to Semitracks at (505) 858-9813, or call (505) 858-0454 to register by phone.

We offer other courses as well as in-house courses. For more information, visit our website at http://www.semitracks.com.


3. Semitracks Segment of the Month

Semitracks’ new and improved online training is convenient, up-to-date, and cost effective. Access the same material presented in our courses whenever you need it, right when you need it without having to worry about the high costs and hassle of traveling. The semiconductor field is an ever-changing one. With access to the most current information, you can stay on top of the new technology. Online training is also very cost effective. For only $500 per year, you gain access to thousands of dollars worth of courses and course material.

Give our online training a try – for free. This month’s topic is an overview of Analytical Characterization Techniques.

There are a wide variety of analytical techniques used to characterize the surface of a semiconductor device. These range from techniques like GDMS, which are sensitive to surface contamination, to SIMS, which allow accurate depth profiling of implanted species. To learn more, click here.

Sign up to access all of Semitracks online training at http://www.semitracks.com/default.htm and “Learn from the Experts” when it’s convenient for you.


4. Technical Tidbit

Standard Cell LIbraries

The most common approach to IC layout is the standard cell approach. This involves creating a library of cell layouts for particular functions. In this example, we show a 2-input NAND gate. The schematic is shown at the left and the corresponding layout is shown on the right. In a standard cell design, all of the cells are designed to fit into channels. Therefore, they are all designed with the same height or pitch. The width of the cell might vary in order to accommodate all of the transistors needed for the gate. Most standard cell libraries consist of 30-60 basic logic gates, such as AND gates, NOR gates, flip-flops, inverters, etc. The metal and polysilicon interconnect are laid out such that the gates take up a minimal amount of room. Rows of standard cells and adjacent routing channels for wiring allow one to build up more complex functions. This layout is automatically done by layout synthesis tools.

5. Our Mission

Education and Training for the Electronics Industry

Semitracks provides education, training, and certification services and products for the electronics industry. We specialize in serving Semiconductor, Microsystems and Nanotechnology suppliers and users. Semitracks Inc. helps engineers, technicians, scientists, and management understand these dynamic fields. We offer courses in Semiconductor Reliability, Test, Packaging, Process Integration, Failure and Yield Analysis, and Focused Ion Beam technology. Learn from the Experts, Semitracks.