2006 July Newsletter

Volume 2, Issue 7

July 2006

Welcome to the Semitracks Online Monthly Newsletter! It is our goal that you find this newsletter interesting, informative and useful. Please email any comments or feedback to This email address is being protected from spambots. You need JavaScript enabled to view it. .


1. Upcoming Courses

Semiconductor Process Integration

Semitracks, along with Semiconductor International, have put together a two-day course on Semiconductor Process Integration for CMOS and BiCMOS Technologies. Dr. Badih El-Kareh of Texas Instruments will give an overview of the process integration challenges associated with today's advanced semiconductor devices. Dr. El-Kareh will cover passive and active components, contact and interconnect issues, isolation technologies such as STI and SOI, transistor integration issues, as well as full CMOS, BiCMOS and high speed bipolar process integration techniques. To learn more, click on the link below to visit the course page.

Process Integration

  • (September 12-13, 2006) - Dallas, Texas

2. Upcoming Conferences

International Symposium for Testing and Failure Analysis

November 12-16, 2006 Renaissance Austin Hotel in Austin, TX

For more information, click here.


3. Course Schedule

Invest in yourself and your staff. Time is running short to enroll in our Summer courses on Packing Technology, Packaging Design, Process Integration, Reliability, and Failure and Yield Analysis. Come and learn from the experts!

Packaging Technology and Challenges

Semitracks, Inc. and Semiconductor International have put together a course which will provide an overview of the current business climate, anticipated trends and the associated impact on assembly/packaging roadmaps. There will be an in depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution.

Packaging Technology and Challenges

  • (September 11-12, 2006) - Dallas, Texas

Packaging Design and Modeling

Semitracks, Inc. and Semiconductor International have assembled a course on IC Packaging Design and Modeling. This course provides an overview of the packaging design process. The course covers current packaging technologies, including chip scale packaging, Ball Grid Array technology and other current concepts. This class focuses on techniques and the importance of thermal and mechanical simulations. Discussions and examples will concentrate on thermal performance simulations, assembly & packaging stresses, package reliability (including solder joint fatigue simulation), and interactions between chip and package. In addition, a special section will be examples of successful wafer level simulations.

Packaging Design and Modeling

  • (September 13-15, 2006) - Dallas, Texas

Failure and Yield Analysis Course

Failure and Yield Analysis is an increasingly difficult and complex process; engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. This is a multi-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure.

Failure and Yield Analysis

  • (September 18-21, 2006) - Boston, Massachusetts

Semiconductor Reliability

Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. Analysis and experimentation is now performed at the wafer level instead of the packaging level. This requires knowledge of subjects like: design of experiments, testing, technology, processing, materials science, chemistry, and customer expectations. While reliability levels are at an all-time high level in the industry, rapid changes may quickly cause reliability to deteriorate. Your industry needs competent engineers and scientists to help solve these problems.

Semiconductor Reliability

  • (September 25-27, 2006) - Boston, Massachusetts

To register for our courses, register online or download the registration form. You can fax the completed form to Semitracks at (505) 858-9813, or call (505) 858-0454 to register by phone.

We offer other courses as well as in-house courses. For more information, visit our website at http://www.semitracks.com.


4. Semitracks Segment of the Month

Semitracks’ new and improved online training is convenient, up-to-date, and cost effective. Access the same material presented in our courses whenever you need it, right when you need it without having to worry about the high costs and hassle of traveling. The semiconductor field is an ever-changing one. With access to the most current information, you can stay on top of the new technology. Online training is also very cost effective. For only $500 per year, you gain access to thousands of dollars worth of courses and course material.

Give our online training a try – for free.

This month's topic is Digital Logic Functions. To learn more, click here.

Sign up to access all of Semitracks online training at http://www.semitracks.com/default.htm and “Learn from the Experts” when it’s convenient for you.


5. Technical Tidbit

Increasing Capacitance

The challenge with DRAM technology is shrinking the feature sizes to increase integration without reducing the capacitance of the DRAM cell. The real trick is that capacitance costs area. Therefore, how do you reduce the area a capacitor occupies without reducing the area on the capacitor? There are two general approaches, either tunnel down into the silicon to create the capacitor, or build up structures above the silicon to create the capacitor. Currently, the industry is moving toward building capacitors above the silicon. These are usually fin-like structures sticking up above transistors, as shown here at the lower right.

6. Our Mission

Education and Training for the Electronics Industry

Semitracks provides education, training, and certification services and products for the electronics industry. We specialize in serving Semiconductor, Microsystems and Nanotechnology suppliers and users. Semitracks Inc. helps engineers, technicians, scientists, and management understand these dynamic fields. We offer courses in Semiconductor Reliability, Test, Packaging, Process Integration, Failure and Yield Analysis, and Focused Ion Beam technology. Learn from the Experts, Semitracks.