Device Recognition Figures
Figure 1
Photograph of an NMOS 64k SRAM showing its various blocks. This photograph serves as a basis for Figs. 2-10. (photo courtesy ICE Corp).
Figure 2
Photograph of an address buffer on the NMOS 64k SRAM showing power, ground and signal lines. (photo courtesy ICE Corp).
Figure 3
Photograph of the address buffer after the IC was stripped to polysilicon. Locations of individual transistors are shown. (photo courtesy ICE Corp).
Figure 4
Circuit schematic of the address buffer. Numbers on the circuit elements correlate to the numbers in Figure 3. (photo courtesy ICE Corp).
Figure 5
Photograph of data-in circuit on the NMOS 64k SRAM showing power, ground and signal lines. (photo courtesy ICE Corp).
Figure 6
Photograph of the data-in circuit after the IC was stripped to polysilicon. Locations of the transistors are shown. (photo courtesy ICE Corp).
Figure 7
Circuit schematic of the data-in circuit. Numbers on the circuit elements correlate to the numbers in Figure 6. (photo courtesy ICE Corp).
Figure 8
Photograph of the data-out circuit on the NMOS 64k SRAM showing power, ground and signal lines. (photo courtesy ICE Corp).
Figure 9
Photograph of the data-out circuit after the IC was stripped to polysilicon. Locations of individual transistors are shown. (photo courtesy ICE Corp).
Figure 10
Circuit schematic of the data-out circuit. Numbers on the circuit elements correlate to the numbers in Figure 9. (photo courtesy ICE Corp).
Figure 11
Graphic sequence describing the major mask levels for a 4 transistor cell 64k Static Random Access Memory (SRAM) manufactured by Fairchild Semiconductor Research Center.
