Deprocessing

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What is a Silicon Etch?

Silicon etches are those etches that are used to assess the quality of the IC active layers. In most cases, defects that are found at this level can be traced to very subtle functionality problems. The most detectable problems can be found on memory devices. For example, in a planar DRAM memory cell, communication between adjacent cells can be caused by stacking faults lying on the field oxide isolation between storage capacitors. Other types of defects, such as implant or diffusion problems, can also be diagnosed using silicon etch techniques. For example, anodic etching (or staining), while commonly done on wafers, can also be done on a single die to inspect implanted or diffused regions.

Why Perform a Silicon Etch?

Silicon etches are used for several reasons. First, the electrical failure on the IC can be diagnosed to the point where all other possible defects can be eliminated. This situation is more common on regular structures like memory devices than on ASIC or analog devices. Second, sometimes the part is deprocessed to the substrate without determining a failure mode. In this case, a substrate decoration may be a last chance at identifying a possible failure mode.

Silicon etches have the ability to identify material defects, including point defects, dislocations, planar defects (stacking faults), and processing anomalies (e.g. areas of different dopant type). Unless the defect is well characterized, the connection between the defects and the electrical phenomenon that has been observed may be unclear. Material defects may indicate general quality issues and may not directly relate to a specific failure, while dopant issues are generally a problem if they are found anywhere on the active area of the IC.

How is a Silicon Etch Performed?

Each etch has its own specific recipe that must be followed to achieve good results and a specific type of defect that can be decorated. Some of the more common recipes are listed below.

Anodic - An anodic etch is a basic acetic acid/ hydrofluoric acid/ water mixture with an electrical potential applied between the sample and a metal (usually platinum) contact. This type of etch is very useful for decorating p and n type areas. An important reminder for failure analysis work (which is usually done on a single die rather than a wafer) is that the contact to the semiconductor MUST be to the front or active side. A good electrical contact can be made via a metal probe or by a spring loaded clip.

Dash - The Dash etch, named after its inventor, W. C. Dash, is primarily used for junction delineation. The junctions are stained according to their doping concentration when held under a strong light source for several tens of seconds. The Dash etch does not accentuate polishing damage. The basic formulation is HNO3:HF:Acetic in the ratio 3:1:12.

Ref: W. C. Dash, Journal of Applied Physics, 27, 1956, p. 1193

Schimmel - The Schimmel etch is good for delineating dislocations, slip planes, swirl defects, stacking faults, and oxygen clusters in <100> material. In essence, this etch is a Sirtl etch that has been buffered with acetic acid. The basic formulation is 75 g of chromic acid (CrO3) dissolved in one liter of deionized water. The amount of hydrofluoric acid (HF 49%) to be added depends upon the resistivity of the material being etched. If the resistivity is above 0.2 W-cm, then add two liters of HF. If the resistivity is less than 0.2 W-cm, add an extra 0.5 liter of water along with the HF. Delineation of the doped regions occurs in about 5 to 15 minutes, with the more lightly doped regions appearing first.

Ref: D G. Schimmel and M. J. Elkind, Journal of the Electrochemical Society, January, 1978, pp 152-155.

Secco - (or Dow etch) The Secco etch can be used to delineate dislocations in <100> and <111> silicon as well as swirl defects, etch pits, stacking faults, and oxygen clusters. However, this technique cannot decorate slip planes. This etch is usually performed with a potassium dichromate (K2Cr2O7) mixed 44 g to one liter of water combined with two liters of 49% HF. This etch is slow to decorate defects unless ultrasonic agitation is used. Normal etch times are about 5 minutes under ultrasonic agitation and about 20 minutes without it.

Ref: F. Secco d'Aragona, Journal of the Electrochemical Society, vol. 119, no. 7, July 1972, p. 950.

Sirtl - As with the Schimmel etch, the Sirtl etch is useful for decorating dislocations and stacking faults in silicon. The basic etch, as defined in their original paper, consists of 46 g of CrO3 in 100 g of 40% HF.

Ref: Von Erhard Sirtl and Annemarie Adler, Z. Metallik, 52, 1961, pp. 529-531.

Sopori - As listed, this is an etch consisting of 36 parts of 49% HF, 20 parts of acetic acid (CH3COOH) and one to two parts HNO3. The etch is listed as a defect decoration etch for polycrystalline silicon.

Ref: B. L. Sopori, Journal of the Electrochemical Society, Solid-State Science and Technology, Technical Notes, March 1984, pp. 667-672.

Wright - The Wright etch is an improved version of the Sirtl etch. The etch decorates <100> and <111> plane defects in both p and n type material over a wide range of resistivity. This is a slow etch requiring about 10 to 15 minutes to bring out most defects. The etch consists of 30 ml of 5 molar CrO3, 60 ml of HF, and 30 ml of HNO3 buffered with 60 ml of glacial acetic acid and 60 ml of water. Copper nitrate of copper sulfate (2 g) is also added for junction decoration.

Ref: M. W. Jenkins, Journal of the Electrochemical Society, 124, 1977, p. 757.

Yang - The Yang etch will decorate all common defects. Hot processing-induced defects appear after about 2-3 minutes and starting material defects emerge after about 10-15 minutes. The etch consists of a mixture of 150 g of CrO3 in one liter of water. The resulting solution should be diluted in an equal amount of water.

Ref: K. H. Yang, Journal of the Electrochemical Society, 131, 1984, p. 1140.

When is a Silicon Etch Performed?

The decision to use a silicon etch is usually made very late in the course of a failure analysis job. The use of such etches implies that all of the material above the substrate has been removed. Before deciding to proceed in this manner, a high degree of certainty that the problem is not in the layers above the substrate is essential. If the problem can be traced to a localized area and other failure mechanisms eliminated, it can be easy to decide the type of defect to look for. For ASIC type devices, decorative substrate etches should only be used when other techniques have been exhausted.

References on Silicon Etching

1. W. C. Dash, Journal of Applied Physics, 27, 1956, p. 1193

2. D G. Schimmel and M. J. Elkind, Journal of the Electrochemical Society, January, 1978, pp. 152-155.

3. F. Secco d'Aragona, Journal of the Electrochemical Society, vol. 119, no. 7, July 1972, p. 250.

4. Von Erhard Sirtl and Annemarie Adler, Z. Metallik, 52, 1961, pp. 529-531.

5. B. L. Sopori, Journal of the Electrochemical Society, Solid-State Science and Technology, Technical Notes, March 1984, pp. 667-672.

6. M. W. Jenkins, Journal of the Electrochemical Society, 124, 1977, p. 757.

7. K. H. Yang, Journal of the Electrochemical Society, 131, 1984, p. 1140.

8. Tutorial notes, IRPS 1984

9. ISTFA Failure Analysis Desk Reference, Supplement 3, March 1993.

10. E. Doyle and B. Morris, Failure Analysis Techniques,

11. D. Platteter, IRPS 1976, p. 248

12. M. Jacques, IRPS 1979, p. 197