Dynamic Voltage Contrast Figures

Voltage contrast image of an unpassivated IC under static operating conditions. (Courtesy Sandia Labs).




Voltage contrast image of the same IC under static operation and the resulting "barber poles". (Courtesy Sandia Labs).




Conceptual diagram of dynamic fault imaging. (Courtesy Intel Corp.).




Voltage contrast image showing two logic states and the subtracted image that shows the differences. (Courtesy Intel Corp.).




Progression of images showing the spread of a logic fault throughout an IC. (Courtesy Intel Corp.).




Voltage contrast image showing voltage change at a step over oxide due to partially open interconnect. (Courtesy Sandia Labs).




Voltage contrast image of a defective bit line on a non-volatile memory. (Courtesy Sandia Labs).




Voltage contrast image of the defective bit line shown in Figure 7 at higher magnification. (Courtesy Sandia Labs).




Voltage contrast image of a simple logic gate in a static condition. (Courtesy DM Data).




Voltage contrast image of the same logic gate in dynamic operation. (Courtesy DM Data).




Voltage contrast image showing the principle of image subtraction to localize a defect. (Courtesy Analytical Solutions).




Voltage contrast image of an ASIC. (Courtesy Analytical Solutions).