External Visual Figures
Figure 1
Reject criteria for external visual examination.
Figure 2
Reject criteria for external visual examination.
Figure 3
Reject criteria for external visual examination.
Figure 4
Reject criteria for external visual examination.
Figure 5
Reject criteria for external visual examination.
Figure 6
Reject criteria for external visual examination.
Figure 7
Reject criteria for external visual examination.
Figure 8
Reject criteria for external visual examination.
Figure 9
Reject criteria for external visual examination.
Figure 10
Reject criteria for external visual examination.
Figure 11
An example of a bad lid seal on an IC. (Photo courtesy Sandia Labs).
Figure 12
An example of contamination on the package. (Photo courtesy Sandia Labs).
Figure 13
An example of the markings you might encounter on an IC. (Photo courtesy Analytical Solutions).
Figure 14
An example of contamination bridging two or more leads on an IC. (Photo courtesy Sandia Labs).
Figure 15
An example of a solder bridge on an IC. (Photo courtesy Sandia Labs).
Figure 16
Low power optical photograph showing an example of markings on an IC. (Photo courtesy Sandia Labs).
Figure 17
An example of a package lid seal gap on an IC. (Photo courtesy Sandia Labs).
Figure 18
An example of a broken lead on an IC. (Photo courtesy Sandia Labs).
Figure 19
An example of a 16 pin ceramic lid flatpack IC. (Photo courtesy Sandia Labs).
Figure 20
An example of a 44 pin leadless chip carrier IC. (Photo courtesy Sandia Labs).
Figure 21
An example of a 24 pin ceramic dual inline packaged (CERDIP) IC. (Photo courtesy Sandia Labs).
Figure 22
Low magnification photograph of a solder bridge on an IC. (Photo courtesy Sandia Labs).
Figure 23
An example of a bad lid seal on an IC. (Photo courtesy Sandia Labs).
