In this section we’ll cover the topic of positive bias temperature instability, or PBTI. PBTI primarily affects transistors that use high-k gate dielectrics. It is receiving more attention as leading edge manufacturers implement high-k metal gate transistor processes. We’ll begin this section with an overview of the properties of high-k dielectrics. High dielectric constant materials behave somewhat differently than silicon dioxide, so it’s important to understand how these differences affect transistor reliability. We’ll then discuss positive bias temperature instability and cover the mechanism, how to model its behavior, and methods to mitigate the problem.
To understand why the industry is using high-k dielectrics in the leading edge devices, we need to back up a step. We are running into a fundamental barrier in transistor operation--a silicon dioxide gate dielectric cannot be scaled any further without serious problems. The gate must be scaled down to properly control the transistor channel behavior. By using ultrathin gate dielectrics, the leakage becomes too high. This means that these devices would not be suitable for any application where power is critical, such as portable applications. Even desktop and server applications are sensitive to this leakage as they raise power usage and generate excessive heat. That means we can’t use oxide thickness as a method to increase capacitance. The solution is to replace the silicon dioxide with an insulating material that has a higher dielectric constant. This provides a higher capacitance, which in turn improves the transistor performance. Unfortunately hafnium-based materials do not bond well to silicon. Therefore we need a buffer layer that bonds both to silicon and to the hafnium oxide dielectric. The best material to do this is silicon dioxide, like we show here.
As of this writing, high-k dielectrics are relatively new in production and still not completely understood. This can be seen in the research studies involving high-k dielectric breakdown. In one model, researchers assume that traps are generated in the high-k layer. Breakdown of the high-k layer then triggers a breakdown of the entire dielectric stack. This model is supported by researchers who have observed what they thought to be trap generation in the high-k material, or at least assumed that was the case. In another model, researchers assume that traps are generated in the interface layer. Therefore, a breakdown of the interface layer triggers the stack breakdown. Researchers who have not observed trap generation in the high-k layer support this model. There are some additional factors that make it difficult for researchers. For instance the stack asymmetry will increase the problem complexity. The silicon dioxide is only on one side of the high-k dielectric, so the response will be different for positive and negative bias. Manufacturers use different materials for their high-k dielectrics, including non-hafnium oxides like aluminum oxide, zirconium oxide, and lanthanum oxide. They also use different deposition techniques like atomic layer deposition, metallorganic chemical vapor deposition, and plasma enhanced chemical vapor deposition. Furthermore, even high-k dielectrics deposited the same way can be different due to slight differences in pressure, temperature, and material crystallization processes. So far, companies have only had a few learning cycles to optimize their high-k processes. Since all of these layers being studied by researchers are different, why wouldn’t their reliability be different as well?
Several manufacturers introduced hafnium-based high-k dielectrics at the 45-nanometer CMOS technology node as a way to reduce gate leakage while maintaining an aggressive electrical oxide thickness or EOT. The penalty for doing this is that there are defects intrinsic to the high-k material, which leads to undesired transport through the dielectric and trapping-induced instability. These fast, reversible charge trapping processes are active in high-k, never observed before in silicon dioxide. This means that threshold voltage instability occurs even at time-zero. Researchers refer to this behavior as hysteresis. There is charge trapping during conventional DC measurements that prevents evaluation of intrinsic films. It also means that there is a need for fast measurement techniques. The complex nature of a multi-layer gate stack dielectric makes understanding phenomena more challenging. For example, is a time zero mobility degradation observed through DC characterization due to charge trapping in the high-k layer or driven by interface properties? The scientific community is still rigorously researching the exact physical and chemical nature of electron traps in the hafnium oxide–silicon oxide structure. The results of ab initio calculations and experimental studies based on electron spin resonance, or ESR measurements have pointed to oxygen vacancies and interstitial oxygen atoms as possible defects controlling the threshold voltage instability. The trap characteristics obtained from time-resolved measurements and defect spectroscopic techniques appear to match O-vacancy defects. Nearby we show data on oxygen vacancies in hafnium oxide materials from two different researchers. These data were obtained through spectroscopic measurements. The oxygen vacancy can have five states (2 minus, 1 minus, neutral, 1 plus, or 2 plus). The Vs represent vacancies, and the Is represent interstitials. The lines represent states, and the dots represent the electrons occupying the state. For the negative states, one can see that an extra level is pulled down from the conduction band. Notice the states near the midgap; these will interfere with Fermi level producing a phenomenon known as Fermi Level pinning.
With the introduction of high-k dielectrics, the phenomenon of positive bias temperature instability has surfaced. Researchers have observed electron trapping and detrapping. This action is quite fast, and has an impact on reliability assessment. There is also instability in the threshold voltage with respect to time. The effect appears to be logarithmic and follows the Power Law. It also appears to have a saturation effect, but researchers are not in complete agreement on these characteristics. Researchers also disagree as to whether there are pre-existing traps, stress-induced traps, or other defects that generate this positive bias. Researchers also disagree about the role of the interface layer, as well as the stress scheme for accurate lifetime projection at use conditions.
Let’s move on and discuss models for Positive Bias Temperature Instability. Accurate PBTI lifetime projections require time, voltage, and temperature dependencies of the threshold voltage shift to be accurately determined. Let’s begin with the time dependence.
The Power Law has been extensively used for modeling NBTI induced threshold voltage instability and has also been found to fit PBTI data in high-k stacks for long-term stress. An accurate extraction of the time power exponent is critical for End-Of-Life projections and requires use of fast threshold voltage measurement methods. The exponential law has also been proposed for modeling PBTI time dependency and predicts a saturation level of the shift, or ΔVmax, for long stress times.
The exponential law may be an optimum modeling choice if electron trapping is the only mechanism determining VT instability and no new traps are created during stress. Caution needs to be exercised to ensure that VT shift saturation levels are not an artifact of relaxation phenomena due to "slow" VT measurements.
There are some techniques to mitigate the effects of PBTI. To first order, PBTI is reduced as the thickness of the high-k layer is reduced. Several researchers have confirmed this behavior. This is because the number of electron traps is reduced for a physically thinner stack. Chad Young was able to verify that the threshold voltage shift is reduced if trapping occurs within the bulk of the high-k dielectric. Scientists at TI postulated that a change in the physical structure, thought to be suppressed crystallization, for thinner gate stacks results in reduced trap densities leading to reduced instability. Engineers have also demonstrated effective ways of minimizing PBTI through process optimization. These improvements have been demonstrated although exact physics behind these effects are still not clear. For instance, in hafnium oxide versus hafnium silicate films, the threshold voltage instability is significantly reduced in hafnium silicate stacks compared to that observed in hafnium oxide stacks. Also, PBTI significantly increases as the hafnium content in the high-k increases. In the case of metal gate versus poly gate, process engineers observe a smaller instability in metal gate based high-k dielectrics like titanium nitride compared to polysilicon gates.
Another interesting effect is that of nitrogen on PBTI. Process engineers have found that the threshold voltage instability improves with increasing content of nitrogen in the stack, and the improvement is more significant when nitrogen is placed further away from silicon substrate. Researchers theorize that the incorporation of nitrogen passivates the oxygen vacancies. Researchers are now looking for further evidence that oxygen vacancies constitute the origin of instability. Fluorine also has an effect on PBTI -- theoretical calculations have suggested that fluorine potentially passivates oxygen vacancies most efficiently. Researchers have also demonstrated that fluorination of hafnium based dielectric results in significant improvement of PBTI lifetime and SILC effect reduction. Here is some data from Tseng showing the improvement in PBTI by incorporating fluorine. The details for the control and fluorinated device are shown in the table at the upper right. Notice in the graph on the upper left that the threshold voltage shift is significantly reduced for the fluorinated device. Also in the lower left, the time to failure for a given device is much longer with the fluorinated device. This gives orders of magnitude lifetime improvement for the fluorinated gate stack.
In conclusion, positive bias temperature instability is a challenging reliability issue for high-k dielectrics in CMOS devices. A variety of techniques are used to characterize PBTI in today’s circuits. It is important to use fast measurement techniques to help determine the slope as electrons move in and out of some traps quite quickly. There are rudimentary PBTI models, but these models need improvement. This is especially true with regards to long term instability and defect generation mechanisms. Finally, an improved understanding of PBTI should lead to improvements process optimization techniques for minimizing this reliability problem.
A technique for increasing Flash memory density is multi-level cells. If one can accurately control the amount of charge on the floating gate, it can be parsed into four or more levels, rather than the standard two levels. In NOR flash memories, channel hot electron programming, under proper conditions, gives a linear relationship with unit slope between programming gate voltage (VGP) and the threshold voltage variation independent of cell parameters. Figure 1 shows ΔVT as a function of the programming voltage for three different channel lengths. One can also plot very similar data in which the number of pulses is used in lieu of the programming voltage. In theory, one could place any given amount of charge on a gate to produce a large amount of possible states, but the current through the cell transistor would be increasingly difficult to distinguish between another.
￼Given this linear relationship, one can devise a series of gate programming voltages to program the cells with different amounts of charge to yield distinct levels within the cell. Figure 2 shows an example of the control-gate voltage pulses. An alternative approach is to use multiple pulses to program the level. While this simplifies the high voltage circuitry, it requires longer writing such a device, as multiple pulses must be used.
The cell current, obtained in reading conditions, can be compared with several currents provided by suitable reference cells. In Figure 3 we show three reference cells. The comparison values are converted to a binary code, whose content can be 11, 01, 10, or 00, due to the multilevel format of the memory. MSB is the most significant bit, and LSB is the least significant bit.
Figure 4 shows the threshold voltage distribution for 2-bit per cell device as compared to the standard 1-bit per cell device. Notice that there is significant margin in the 1-bit per cell device. In the 2-bit per cell device, there is considerably less margin. Notice also that the 11, 10, and 01 cell distributions give rise to different current distributions, measured at fixed read voltage, while the 00 cell distribution does not drain current as well as the programmed level of a standard 1-bit per cell device.
Q: I am seeing an I-V curve for an IC between VDD and GND that looks like this (see figure below). What creates the momentary drop in the upper right?
A: Several things might cause this behavior. One item you might want to check is to see if you have good continuity. Intermittent continuity could create this type of curve. A second possibility (more likely) is that you are attempting to power up a device without properly tying the input pins to either ground or VDD. You should tie all floating inputs to either ground or VDD to prevent unstable leakage during power-up. A third possibility is that the IC is experiencing some type of internal bus contention at lower voltages. One side of a bus may power up into a state opposite the other side of the bus, causing increased current. This can then resolve itself as the voltage increases on the internal components.
(Click on each item for details).
Semiconductor Reliability on March 12-14, 2012 (Mon.-Wed.) in San Jose, CA, USA
Wafer Fab Processing on March 12-14, 2012 (Mon.-Wed.) in San Jose, CA, USA
Copper Wire Bonding Technology and Challenges on May 7-8, 2012 (Mon.-Tues.) in Munich, Germany
Failure and Yield Analysis on May 7-10, 2012 (Mon.-Thurs.) in Munich, Germany
Semiconductor Reliability on May 14-16, 2012 (Mon.-Wed.) in Munich, Germany
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