In this section we will discuss underfills and their use in the electronics assembly process. Underfills are a class of polymers used to help enhance the connection between the die and the substrate. With the advent of solder bumping and BGA packages came the need for underfills. First, we will discuss why underfills are needed. Next, we will discuss the underfill process. Finally, we will discuss the reliability of underfill materials.
BGA underfills are now commonly used for chip-on-board as well as BGA and Chip Scale Package mounting. The underfill helps to distribute the stress evenly across the die, making the solder joints more reliable. It can also provide mechanical strength to a portable system, such as a cell phone, PDA, or other portable device. Because the underfill holds the component rigidly in place on the board, it can also improve the electrical conductivity of the solder joints. Finally, underfills can be used to protect the surface of the die.
The electronics industry increasingly uses flip chips and chip-scale packages in electronic assemblies for portable devices. An early decision engineers must make is the choice of the underfill material. Underfills without filler particles flow more rapidly, but have higher coefficients of thermal expansion. Underfill with filler particles flow more slowly, but have lower coefficients of thermal expansion and better shock-absorbing properties. Several considerations are involved in the design of a board using flip chips or chip-scale packages that will be underfilled. One significant consideration is component density. Components that are placed close to a component that is being underfilled may either draw fluid underfill away from the target component, or assist keeping the fluid underfill in place. Fluid underfill that flows to adjacent components generally causes no harm to the adjacent components, but it subtracts underfill from the precisely measured quantity delivered to the target component. Underfill that flows to adjacent components may also make rework far more difficult.
This diagram shows the basic ball grid array underfill process. First, one begins by dispensing flux on the surface of the substrate. This will help ensure the solder makes adequate contact to the solder pads on the board or substrate. Next, the chip is placed over the appropriate pads. Alignment is critical to help ensure a proper solder joint is formed. Next, the assembly is heated to reflow the solder. This can be done using hot air, infrared heating, vapor phase, or other methods. Next, the underfill is dispensed. There are two different methods for achieving a proper underfill. One is to dispense the epoxy at one end of the chip and allow capillary action to pull the epoxy under the entire part. The other method is to put epoxy on the chip before mounting it to the board or substrate. Many manufacturers are turning to the latter method, since the throughput is higher and the cost is approximately 60% less than the conventional capillary action method. After the underfill is dispensed, one can deposit fillets on the side to provide additional mechanical strength and help reduce stress. Finally, the epoxy is cured, resulting in an assembly that is mechanically strong.
One of the main reasons the electronics industry uses underfills is to improve the reliability of the solder joint. The underfill helps to distribute stress and hold the solder bump in compression to maintain a more permanent connection to both the board and the chip. Engineers use a standardized test from JEDEC known as the drop test to demonstrate reliability. The test involves placing the board assembly in various orientations on a base plate mounted to a drop table. A motor raises the drop table to specified heights depending on the service condition, and releases the drop table onto a rigid base, creating a large mechanical shock. The data in the chart above shows how an underfill will improve the reliability by a factor of 2 to 10.
Snapback is a less studied phenomenon, but has been receiving more attention recently as a component of ESD research.
Snapback is the forward-biasing of the parasitic npn transistor that exists in the n-channel MOSFET structure. This cross section shows the location of the parasitic npn structure.
The snapback phenomenon was first reported by Albert Ochoa and his colleagues at Sandia National Laboratories in 1983. They observed circuits entering a high current condition when exposed to an ESD event. The circuit configuration precluded the possibility of latchup, so they investigated it further. When an ESD pulse reaches the drain of an n-channel transistor, the avalanche voltage is exceeded. This generates hot carriers, a portion of which are injected into the oxide, and another portion of which are injected into the well. The drain voltage increases until the well voltage is greater than the turn-on voltage of the parasitic npn transistor. The source then injects carriers into the well, lowering the drain voltage and causing the device to go into a negative resistance region. If the drain voltage is greater than the snapback holding voltage, the device will continue to conduct current. If the drain voltage continues to increase, the transistor can be forced into second breakdown where the intrinsic carrier density exceeds the doping levels. Aluminum and silicon melting can ensure if the supply current remains connected and can deliver the current.
This diagram depicts the carrier flow during snapback. Initially, the drain avalanches along the entire perimeter. The hole current flows into the substrate and the electrons flow back into the drain. As the source becomes forward-biased, it begins to inject electrons in to the channel region. The bipolar current adds to the avalanche current near the source region. The drain-to-source voltage drops and the drain remains in avalanche only near the channel region. As the snapback event progresses, the focused drain avalanche current increases the emitter injection. The added carriers drop the resistance of the intrinsic base region and the substrate terminal current drops due to shunting by the base region into the emitter region.
Q: What is the biggest reliability risk for Light Emitting Diodes (LEDs)?
A: In general, allowing the LED to run too hot is the biggest reliability risk. Many important semiconductor degradation mechanisms in LEDs, like dark line defects and encapsulant yellowing, accelerate with temperature. Therefore, running the LED at as low a temperature as possible will help reduce the progression of these failure mechanisms, and lead to a longer lifetime and better reliability.
Please visit http://www.semitracks.com/courses/processing/introduction-to-processing.php to learn more about this exciting course!
(Click on each item for details).
Introduction to Processing on March 7-8, 2016 (Mon.-Tues.) in Shanghai, China
CMOS, BiCMOS and Bipolar Process Integration on March 21-22, 2016 (Mon.-Tues.) in Albuquerque, NM, USA
Wafer Fab Processing on March 29-April 1, 2016 (Tues.-Fri.) in San Jose, CA, USA
Failure and Yield Analysis on May 17-20, 2016 (Tues.-Fri.) in Munich, Germany
EOS, ESD and How to Differentiate on May 23-24, 2016 (Mon.-Tues.) in Munich, Germany
Semiconductor Reliability and Product Qualification on May 30-June 2, 2016 (Mon.-Thurs.) in Munich, Germany
Advanced Thermal Management and Packaging Materials on June 7-8, 2016 (Tues.-Wed.) in Albuquerque, NM, USA
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