In this article we’ll spend our time discussing the major subsystems that are part of an ion implanter. For more details, the reader is encouraged to read Microchip Manufacturing, and Silicon Processing Volumes 1 and 4 by Stan Wolf, and Semiconductor Manufacturing Technology by Robert Doering and Yoshio Nishi.
The major components of an ion implanter are listed here. They include:
We will cover each of the elements in more detail in the following slides.
Figure 1, Model of a typical high current implanter (image courtesy Axcelis).Let’s begin with ion generation and extraction. An ion implanter requires a source of ions to implant into the wafer. This is typically done through a gas field ion source. One can use a low-pressure gas, or one can create a gas by heating solid materials. Some common gases include boron trifluoride and phosphine, while materials like arsenic and antimony oxide can be heated to create a gas. The ion source then ionizes the gas, creating plasma, which contains the dopant ions of interest. An extraction electrode uses an electric field to extract ions and focus the ion beam. The extraction energy of the beam is given by this equation, where q is the quanta of charge, which include ion charge state, and the extraction voltage in kilovolts.
The extraction field extracts all ion types, so it is then necessary to select the ion of interest. We do this using mass analysis. Mass analysis is the process of separating elements or isotopes by mass using an analysis magnet. This will depend on the mass-to-charge ratio. By placing an aperture at correct position at the end of the analysis magnet, one can choose the species of interest. We can identify the species of interest by using this basic equation:
where r sub zero is the radius of curvature of the ion going through the analysis magnet, H is the magnetic field, m is the ion mass number, V sub e is the extraction voltage, and q is the ion charge state.
Figure 2 shows the basic configuration of the mass analyzer. As the ion leaves the ion source and accelerates toward the anode, it gains a certain energy and velocity based on its mass, charge, and the accelerating voltage. The ion is steered by the magnetic force F sub m through the magnet to the mass- resolving aperture. The aperture can be moved to select the ion mass and charge of interest.
After emerging from the magnetic analyzer, ions can be accelerated or decelerated to the appropriate implant energy. This is also known as post acceleration. The total ion energy can be given as this equation,
where q is the ion charge state, V sub e is the extraction voltage between the ion source and the anode, and V sub a is the accelerating voltage, or decelerating voltage on the electrodes.
The next major subsystem is the scanning elements. Once the appropriate ion has been selected, the beam must be rastered across the wafer surface. This needs to be done with a uniform density and a constant angle of incidence to give a parallel scan. This is important so that the channeling effects are consistent across the wafer. The ion beam can be rastered as either a spot beam or as a ribbon beam. A ribbon beam tends to work better for smaller technologies where beam spreading due to charging is a problem. The beam can be further shaped by electrostatic and/or electromagnetic lens. For instance, one might prefer an elliptical shape or a non-Gaussian beam for certain designs. The scanning can also be used to define the implant angle. Zero degrees and seven degrees are popular implant angles. For instance, 7° is used because it limits ion channeling significantly. Another popular technique is to use large angles between 20 and 60°C for lateral asymmetrical channel and halo implants.
Ion implantation can be done with electrostatics, electromagnetics, mechanical scan, or a mixture. In electrostatic or electromagnetic scanning, the wafer is held stationary and the beam is scanned in the x- and y-axes. This is typically used in a single wafer process. In contrast, mechanical scan is used for batch wafer processing. The beam is fixed and the wafers are scanned through the beam in the x- and y-axes. There are also hybrid-scan systems that use electrostatic or magnetic scans in one axis and mechanical scans for the other axis. In a ribbon scan system, the ribbon beam is set to be greater than the wafer diameter and the wafer is scanned mechanically through the beam in the other axis. There are also newer techniques like radial scanning used today as well.
Figure 3 shows a typical configuration for electrostatic scanning. After the beam emerges from the mass analyzing magnetic and resolving slit, the beam is focused and then passed through a scan generator. The beam is then run through a beam parallelizing system that creates a parallel beam for the wafer surface, resulting in a more uniform implant.
Figure 4 shows an example of a spinning disk arrangement for mechanical scanning. The wafers are placed on the pads and then rotated through the beam. Simultaneously, the disk moves back and forth to produce an additional axis of scan. The disk can also be tilted to produce an angled implant.
Scanning can also be done through magnets. Figure 5 shows an example of a ribbon beam that is scanned using a magnet. The wafer holder shown at the bottom right provides a second axis of scan.
Dose measurement is usually done with a Faraday cup. A Faraday cup is a structure that captures the incoming electrons or ions and bleeds the charge off through a grounded plate to a current meter. One can integrate the current over time to compute the dose. The dose φ is given by this equation
and is a function of the beam current, implant time, ion state, charge, and implant area.
Another important system in the ion implanter is the charge control system. This system minimizes charge build-up on the wafers, which can lead to ESD damage on sensitive gates. Excess charge can also lead to charge spreading, which creates non-uniform lateral and vertical doping profiles as well as dosimetry errors. Charge control is typically accomplished using a plasma tube, which creates numerous low energy electrons or ions in front of the wafers that neutralize the doping species.
Another important component of the system is wafer handling. Wafers are transferred from Front Opening Unified Pods, sometimes called FOUPS by industry personnel, into the implanter, where the machine performs the implant, and back out. Precision, repeatability, and minimal contamination generation are critical for this process. This photograph shows the interface for the FOUPS or cassettes on the front of the machine.
Another critical system is the high vacuum system within the implanter. It is important to minimize collisions between air molecules and the ions, so engineers maintain the vacuum at better than 10-7 - 10-8 torr to prevent these collisions. This also helps to minimize charge neutralization that can occur as a result of these collisions.
Finally, monitoring and control is a big component of today’s ion implanters. Computer systems within the implanter monitor and control all aspects of the operation, including the user interface, recipe management, data management, preventive maintenance schedules and error logging. This is all essential for good process control within the fab.
Next month, we’ll cover ion implantation process issues.
Some of you might have heard of the term Transene etch and wondered exactly what it was. Transene is actually a company based in Danvers, Massachusetts, that manufactures a variety of chemical etches (http://www.transene.com/). In the semiconductor industry, labs make use of several of their etchants.
One of the more common etchants used in failure analysis work is their copper etch APS-100. APS 100 from Transene is a commercial mix of 15 – 20% (NH4)2S2O8 + H2O. This reaction of ammonium persulfate and copper follows this equation:
Cu(s) + (NH4)2S2O8(aq) -> CuSO4(aq) + (NH4)2SO4(aq).
It etches copper at a rate of approximately 80Å̊/sec at 40°C. This mixture works well to remove copper layers on an integrated circuit. It does not have the control necessary for removal during the fabrication process, but it does do a good job of clearing an area for inspection of lower layers. You can also use photoresist as a mask for the etchant.
Another common etchant used in FA is their aluminum etchant Type A. Type A is a mixture of 80% H3PO4 + 5% HNO3 +5%CH3COOH + 10% H2O (phosphoric acid + nitric acid + acetic acid + water). It etches aluminum at a rate of approximately 80Å̊/sec at 40°C. You can also use negative photoresist as a mask for the etchant.
Q: I need to distinguish unambiguously between LOCOS and STI, particularly in the case when you can not compare between them, but need to know which type. The “birds beak” effect is not very clear in most cases. Please, advice what other ways to certainly identify each of the types. I will appreciate your thoughts.
A: A couple of thoughts come to mind. Usually the trench for STI will be etched deeper into the silicon. Remember that LOCOS consumes silicon, so about 45% of the oxide grows down into the silicon while the upper 55% will be above the original surface. The trench sidewalls will be steeper than the LOCOS sidewalls. Of course, you'll need to cross-section the device to see these items. For a top-down assessment you might be able to determine this optically, but it will be difficult on a modern technology. Because the oxide extends above the surface, features on the oxide may not be in focus at the same time as features directly on the silicon. You could possibly see this effect on the polysilicon while viewing at high magnification.
A reader wrote in concerning last month's "Ask the Experts" column and brought up a good point regarding interpretation of the I-V curve. Here is his response:
I think you missed the obvious on your answer in the "Ask the Experts" question. It could be a lot of things, but if it was a CMOS device, then one thing that should be noted is that a CMOS inverter always shows this effect. The NMOS and PMOS transistors have their gates tied together in the CMOS inverter. If the common gate starts at zero and is ramped up, initially, the PMOS transistor is on but the NMOS is off showing little current through the two transistors in the inverter. As the gate voltage increases, the NMOS transistor turns on and current is then pulled between VCC and GND. Eventually, the PMOS transistor will turn off reducing the power supply current again. Thus, it is a common occurrence to see this "middle" area with higher current. The actual circuit analysis will be much more involved, so the full answer can not be given without knowledge of the circuit, but high current with the voltage between the NMOS Vt and the PMOS Vt is not unusual.
Please visit http://www.semitracks.com/courses/packaging/copper-wire-bonding-technology-and-challenges.php to learn more about this exciting course!
(Click on each item for details).
Copper Wire Bonding Technology and Challenges on May 7-8, 2012 (Mon.-Tues.) in Munich, Germany
Failure and Yield Analysis on May 7-10, 2012 (Mon.-Thurs.) in Munich, Germany
Semiconductor Reliability on May 14-16, 2012 (Mon.-Wed.) in Munich, Germany
Wafer Fab Processing on June 5, 2012 (Tues.) in San Jose, CA, USA
Reliability and Characterization Challenges on June 11, 2012 (Wed.) in San Francisco, CA, USA
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