ESD in Nanostructures

Electrostatic Discharge (ESD) phenomenon today is a reliability concern in semiconductor components, systems from cell phones, laptops, to automotive products. A key question today in the semiconductor industry is whether ESD sensitivity will be a roadblock to the introduction, manufacturability or implementation of today’s technology, and of future nano-structures? A first question - Is this an issue in the future, or are we already in the ESD roadblock condition today? To start this dialogue, we must ask where we are today in the present technology, and what is the technical trend that we are experiencing in the electrostatic sensitivity.

In this talk, we will discuss the direction of semiconductor technology from digital, analog and radio frequency (RF) applications. We will first discuss CMOS technology and the ESD Technology Roadmap highlighting the trend in the semiconductor industry; this will be followed by a discussion on the trend in CMOS, Silicon on Insulator (SOI), strained Silicon, to FINFET devices. For RF technology, ESD trends and advances in RF CMOS, BiCMOS Silicon Germanium, Silicon Germanium Carbon, Gallium Arsenide, and RF MEMs will be reviewed. The presentation will also include the magnetic recording industry’s transition from MR, GMR to tunneling MR (TMR) heads. ESD issues associated with photomasks, and reticles in the mask product process will also be highlighted. Off-chip protection concepts such as polymer voltage suppression (PVS) devices will also be discussed.

In the talk, we will also address some fundamental questions on ESD. Will we need to lower the ESD standards? What is the impact on system developers? What is the implication for the manufacturing of nano-structures? What does the magnetic recording industry know that the semiconductor industry does not? What does this mean for manufacturing science and materials? What is the global implications of quality and reliability?

Register for this Course

Course Dates | Location

Request a date for this 1-hour webinar.



Pay Via Credit Card

Add To Shopping Cart

Pay Via Purchase Order/Check

Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.

Please email the printable registration form for public courses to us at the email address on the form to complete your order.

Additional Information

If you have any questions concerning this course, please contact us at

Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.


Dr. Steven H. Voldman

Steve Voldman

Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge protection in semiconductor chips. His IEEE Fellow citation is for "contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology." He received his B.S. in Eng. Science from Univ. of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Eng. Physics (1986) and a Ph.D EE (1991) from Univ. of Vermont under IBM's Resident Study Fellow program. Dr. Voldman was a member of the semiconductor development of IBM for 25 years. He was a member of the IBM's Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS and Silicon Germanium, RF CMOS, RF SOI, smart power technology development and image processing technology teams. In 2007, Voldman joined the Qimonda Corporation as a member of the DRAM development team, and reporting to Qimonda Europe working on 70, 58, 48 and 32 nm CMOS DRAM technology. He was responsible for ESD technology strategy, ESD and latchup design manuals, and ESD design working on ESD protection in 512 Mb, 1 Gigabit, and 2 Gigabit DRAM products. In 2008, Voldman worked as a full time ESD consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) supporting ESD and latchup development for 45 nm CMOS technology and a member of the TSMC Standard Cell Development team in Hsinchu, Taiwan. In 2009 to 2011, Steve was a Senior Principal Engineer working for the Intersil Corporation working on analog, power, and RF applications in RF CMOS, RF Silicon Germanium, and SOI. In Intersil Corporation, Steve was responsible for ESD corporate strategy, ESD CAD development, ESD parameterized cell development, latchup, documentation development, ESD design reviews, and wide range of product development in analog, power, and mixed signal applications.

Dr. Voldman was chairman of the SEMATECH ESD Working Group, to establish a national strategy for ESD in the United States; this group initiated ESD technology benchmarking strategy, test structures and commercial test system strategy. At SEMATECH, he was responsible for establishing collaboration between the ESD Association and the JEDEC standards development, as well as launching the first TLP standard working group. He is a member of the ESD Association Board of Directors, ESDA Education Committee, as well ESD Standards Chairman for TLP and VF-TLP testing. Dr. Voldman was also the first chairman of the ESDA ESD Technology Roadmap committee and co-established the ESD Technology Roadmap in 2005. In 2005, he was the Subcommittee Chairman for both the Latchup Sub-committee for the International Reliability Physics (IRPS) and the EOS/ESD Symposium, the ESD Chairman for the International Physical and Failure Analysis (IPFA) Symposium, and presently serving on the technical program committees for the Taiwan ESD Conference (T-ESDC) 2010 in Taiwan, and ICSICT 2010 in China. Steve has provided tutorials on ESD, latchup, failure mechanisms, and RF ESD devices to the IRPS, EOS/ESD, T-ESDC, BCTM, IPFA, ASICON (China), and ICSICT (China). He was the recipient of the ESD Association Outstanding Contribution Award in 2007.

Dr. Voldman is an author of the six books ESD: Physics and Devices, ESD:Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, and ESD: Failure Mechanisms and Models, ESD: Design and Synthesis as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design, and a chapter contributor to new text Nanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In 2011, Dr. Voldman is presently writing new ESD text books to extend the John Wiley and Sons Ltd ESD book series to be released at a future date.

In the ESD Association, Voldman initiated the "ESD on Campus" program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 35 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, and China. He also provides tutorials internationally on ESD protection. Dr. Voldman has written over 150 technical papers between 1982 and 2007. He is a recipient of over 215 issued US patents. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents; and has also founded a limited liability corporation (LLC) consulting business supporting ESD design, teaching, patents and patent litigation. S. Voldman served as the ESD expert witness for Acer vs Hewlett Packard, as well as other patent litigation cases.