Feature Article - Soft ESD Failures, Part 1 - By Christopher Henderson

This article is the first in a two-part series on recoverable failures related to package charging. Sometimes, these failures are referred to as soft electrostatic discharge (ESD) failures. In a soft ESD failure, components with an electrically verified failure unexpectedly recover during the course of the analysis. Recovery can happen during an electrical retest after decapsulation, an electrical retest after bake, or an electrical retest after x-ray.

Soft ESD failures can be frustrating to identify. Some of their common attributes include the following:

• High fallout rates at printed circuit board assembly.
• Burn-in-induced failure in some high voltage plastic-packaged components.
• An electrical signature indicating an elevated power down current, standby current, or quiescent power supply current (IDDQ).
• Leakage on some I/O pins, indicating transistor channel leakage.
• Hard ESD failures occurring with soft ESD failures.
• Partial or complete component recovery after decapsulation.
• Recovery of hermetic package after x-ray radiography but not after bake.
• Recovery of plastic packages after both bake and x-ray.
• Recovery of plastic packages after removal of the component from the printed circuit board.

Soft ESD failure mechanisms have been observed in both hermetic and plastic packages. In hermetic packages, the die is packaged inside a cavity with an inert environment, typically a low humidity nitrogen gas. The package construction uses ceramic or metal and prevents moisture and contamination from entering the cavity.

Plastic packages are non-hermetic. Over time, moisture and contamination can penetrate the epoxy thermoset to reach the surface of the die. Failure analysts have observed soft ESD mechanisms attributable to freeze spray and sandblasting in hermetic packages and component handlers in plastic packages.

Three significant conditions can cause soft ESD failures in hermetic components. At the International Reliability Physics Symposium in 1978, Murray Woods and Gary Gear published work on the role of freeze spray application in soft ESD failures. Additionally, in the early 1980s, engineers at Signetics documented problems with the sandblast process and the use of ungrounded rails in IC handlers.

Figure 1 illustrates the failure model for soft ESD in a hermetic package. Freeze spray, sandblasting, or an IC sliding down the handler plastic tube introduces a significant charge onto the surface of the package. The insulating materials can in turn lead to a high voltage, sometimes in the thousands of volts. The electrical properties of the package, hermetic air gap, and IC materials all affect the final voltage at the IC level. Capacitance is a function of the dielectric constant of the material, the area of the material, and its thickness. In Figure 1, the specific capacitances of the ceramic, air gap, and top glassivation layer on the IC lead to a given voltage on the IC.

In a simplified model, the hermetic package and die can be represented by three capacitors in series. Basic electronics theory teaches us that voltage divides according to 1/C. The passivation layer has the largest capacitance and is essentially ground. The lid has a higher dielectric constant and, therefore, a larger capacitance. Because less voltage drop occurs across the ceramic lid than across the air gap, the largest voltage drop occurs across the cavity. Now, the cavity ambient environment is at a reduced atmospheric pressure. The breakdown voltage is approximately 15 kV/cm in an air environment. Since the air gap is only about 1mm, a corona discharge can occur in the cavity. The negative charge associated with the discharge event drifts to the most positive potential: the bond wires and the passivation layer.

The table in Figure 3 shows capacitance per unit area, dielectric constant, thickness and breakdown voltages for the air gap, glassivation layer, and ceramic lid materials. The table uses the electrostatic unit of charge (esu), also called the statcoulomb. All the other esu units are defined in terms of the esu unit of charge and the centimeter, gram, and second.

Figure 4 illustrates the electrical charge influence on a transistor in a junction isolated IC. At the beginning of the process (see left-hand image), the top of the ceramic lid charges negative. The ceramic and air gap initially stand off the high voltage. However, as the voltage on the ceramic lid increases, the voltage across the air gap exceeds the breakdown voltage, resulting in a corona discharge. After the discharge, a negative charge occurs on the top of the glassivation layer (see center image). The charge on the glassivation layer inverts the lightly doped n-epitaxial layer below the surface, resulting in leakage or, in severe cases, functional failure. When a positive charge is applied to the lid of the ceramic (see right-hand image), the epitaxial layer is not inverted. However, if the epitaxial layer is inverted, the positive charge can cause IC recovery.

In 1978, scientists at Intel discovered that certain Electrically Programmable Read Only Memories (EPROMs) would fail when subjected to freeze spray. Freeze spray is sometimes used to cool devices individually on an ad-hoc basis. After a lengthy analysis, they traced the problem to charge buildup on the lid. The charge was placed on the lid by friction created when solid carbon dioxide particles impacted the ceramic lid. The charge broke down the air gap within the package and deposited charge on the surface of the die, affecting memory cells. Additionally, deposited charge on the die surface created an N inversion layer in the structure, resulting in leakage.

The Intel scientists discovered that EPROM devices recover when illuminated with ultraviolet light through the programming window. Furthermore, they discovered that ultraviolet light is effective when the energy is greater than 4.3 electron volts. They also discovered that devices recover when they are decapped and the die is rinsed in water or isopropyl alcohol. Figure 7 shows the silicon-silicon dioxide band diagram for the basic structure. If the ultraviolet light energy is greater than 4.3 electron volts, it can raise the energies of the carriers to the point where they can overcome the barrier.

In 1983, engineers at Signetics discovered a similar charging problem with sandblasting operations. In this case, Signetics engineers grounded the components in socketed boards to prevent electrostatic discharge. Although some failures still occurred, they manifested themselves differently than typical ESD failures. The failures showed 500 ohm shorts between the supply voltage and ground. After partial recovery, the leakage curve exhibited a parabolic shape, indicative of transistor channel leakage. When delidded, the short on the components recovered. When the lid was cracked, exposing it to air more slowly, the short slowly recovered. The engineers noticed that the short did not recover when delidded in a dry nitrogen environment, leading to the conclusion that moisture in the air helped the shorts to recover. Engineers also noticed that the shorts did not recover with a 150 degree centigrade bake, but would recover when x-rayed for 3 minutes at 70kV accelerating voltages in the x-ray system.

The engineers then attempted to replicate the failures. They found they could replicate the symptoms by using a probe to place -100 volts on the top of the glassivation layer. They could also replicate the problem by applying a large negative voltage to the lid of the component. The failure recovered when they placed a large positive voltage on the lid of the component. Finally, they reproduced the failure symptom using a ZeroStat charge gun on the lid of the component.

The two sets of current-voltage (I-V) curves opposite illustrate the leakage. The curves on the left indicate increasing leakage when -4kV is placed on the lid of the component. The curves on the right show increasing leakage when varying voltages are applied to a droplet of insulating material on top of the glassivation. Leakage becomes apparent when the voltage is less than -25V.

Historically, many scientists assumed air friction caused positive triboelectric charging. The table on the far right indicates the triboelectric charging potential for a variety of materials. Scientists like Baumgartner postulated that air may be misclassified. Tests made by flowing air over a range of surfaces found very little voltage buildup. Some hot air sources were found to be charge generators, possibly due to the nature and temperature of the heating element. Hot plastic was found to be particularly susceptible to triboelectric charging. Positive elements give up electrons, but in air, the dust may be a factor. Large amounts of dust are generated during the sandblasting process. The heating coil material may also be a factor. For more information, see G. Baumgartner "The Misconceptions of Air Flow as A Tribocharging Source," EOS/ESD Symposium, 1992, 1.2.1.

A third well-documented incident involving recoverable failures due to charging was publicized in the late 1980s by Signetics. In this case, Ceramic Dual Inline Packages (CERDIPs) were loaded into an IC handler with ungrounded rails. The rails were improperly grounded because of a missing ESD kit. Signetics experienced high fallout rates for 8-Bit Digital to Analog Converters (DACs) intermittently for years until the problem was isolated. The ICs failed a reference voltage test where the voltage fluctuated as a function of the power supply voltage. These components would then recover when decapsulated or x-rayed. Again, the situation occurred because of triboelectric charging.