This month we continue our overview of ion implantation. This month we are addressing processing issues associated with ion implantation.
In this article, we will discuss charge neutralization, energy contamination, wafer charging, wafer heating, photoresist outgassing, implant angle effects, and ultrashallow junction formation.
The first process challenge we’ll discuss is charge neutralization. We know that the ions need to maintain a specific charge state during the implant process. However, these ions can be neutralized by collisions with gas atoms in the chamber. This is a big problem during boron deceleration, which is used in some implant systems to create shallow junctions. Neutral atoms are a problem because they cannot be accelerated and steered properly with electrostatic plates. They will not be implanted to the correct depth if the neutralization occurs early on; they will not be spread uniformly across the wafer if the system employs electrostatic scanning, and they will not be counted by the dose measurement system.
A different problem happens at higher energies – collisions between ions and atoms can cause increased ionization. The solution is to remove, as much as possible, the atoms from the chamber. This means ultra high vacuum is required in the beamline and in the chamber. This in turn means that one must use high capacity pumps and perform frequent regeneration of cryopumps. One should also avoid decelerating the beam, and one should provide neutral traps or beam filters to remove neutral species.
Charge neutralization brings up a broader issue, that of energy contamination. This situation occurs when ions of the wrong energy are implanted. This leads to incorrect doping profiles. The main causes are charge neutralization, which we discussed, and contaminants of the same mass-to-charge ratio not being removed by the mass analysis magnet. An example of this would be a double-charged dual phosphorus ion in a single-charged single phosphorus ion beam. One would use the same solutions for this problem as with charge neutralization.
Another concern is contamination control. Contaminants can come from apertures, wafer holders, and metals used in the beam line hardware. They can also come from other dopant atoms used in the system that have been implanted into the hardware and then resputtered. And they can come from particles of material flaked off from the beamline hardware or wafer handling system and then transported in the beam by the electrostatic forces. This problem can be minimized by routine cleaning of the components, using materials with low sputter yield in the beamline like carbon, and dedicating implanters by species to prevent cross contamination.
Another significant problem is wafer charging. This can result in device damage due to ESD as charge builds up in sensitive gates. It can also result in non-uniformity, due to the charge on the surface distorting the incoming beam. This is typically a problem with high current implanters. One solution is to use a system to reduce wafer charge. A common method is to use a plasma flood gun. This produces low energy electrons at the surface that can recombine with the charged ions. The goal here is to balance the charge and charge flow at the surface. Another solution is to minimize the beam density by employing dual mechanical or ribbon scanning methods, moving to batch processing to increase the implant area, and increasing scan speeds to lower dwell times. This reduces the time for charge buildup.
Another significant problem is heat generation. High-energy ions decelerate in the wafer, and much of that energy is dissipated as heat. This excess heat can damage photoresist masks, leading to critical dimension changes, or even blistering, flaking or popping. High temperatures can also lead to dopant redistribution, as diffusion processes accelerate exponentially at higher temperatures. This can also lead to undesirable forms of crystal defects. This is mainly a problem with high power, high mass implants where the energy dissipation is significant. The equation below helps to illustrate the dependence on both accelerating voltage and current.
The solutions for this problem include proper wafer cooling, performing hard bake or other resist stabilization techniques, minimizing the power density with larger beam sizes, faster scanning, and so on.
Still another problem is photoresist outgassing. Energetic ions will break the resist polymer bonds, releasing hydrogen. This problem is strongly related to beam power density. The increased heat makes the resist more susceptible to this problem. There are two main issues here. One is charge neutralization, and the other is resist mask damage. Liberated hydrogen will interfere with charge neutralization efforts. The solutions here are to optimize the resist process through hard bakes or ultraviolet photostabilization, increasing the equipment chamber size to reduce local hydrogen concentrations or use high pump speed vacuum systems, minimizing the beam power density, and conditioning the resist through a controlled ramp-up of beam current for example.
Implant angle effects also pose a challenge for process integration. There is beam shadowing that occurs in the channel from 7° implants, a common angle that helps minimize ion channeling. This leads to non-symmetrical channels under the mask edge. This can be addressed through quad implants or through zero degree implants. Some newer implanters can also achieve these effects through beam steering. Another implant angle effect is variation in implant angle in a batch processor. Wafers at the outside receive a different angle implant than those at the center. The solution here is to go to a single wafer implanter with parallel scan to minimize the effect.
Figure 1 groups most common implant applications together so that we can visualize the differences. The chart shows the applications as a function of energy and dose. We start with the highest dose, lowest energy implants, moving toward the lower dose, high energy implants. High current implants are typically done close to the surface, and are done later in the process, so one requires heavier doping to overcome the doping from previous implants. Medium current implants are performed to create the transistor wells and isolation regions, and to determine the transistor channel properties. High energy implants are done to create isolation regions, wells, and deep wells for some types of bipolar or BiCMOS transistors. They can also be used for charge-coupled device structures.
Medium current implants are used for both well and channel engineering. Channel engineering is used to control the drive characteristics of the transistor, and well engineering is used to control the isolation between transistors. The three common channel engineering implants are the halo implant, the threshold adjustment implant, and the super steep retrograde or SSR implants. The three well engineering implants are for shallow wells, deep wells, and channel stops.
Some medium current implants, their dose ranges, energy ranges, and tilts are given in this table. Medium current implants can include layers done close to the surface, like halo implants or threshold adjust implants, or layers put in further below the silicon surface, like deep well structures.
High dose applications are used for heavily doped regions. These include source-drain regions as well as their extensions, polysilicon gate doping, and pre-amorphization implantation.
A final remaining challenge is ultra-shallow junction or USJ formation. Ultra-shallow junctions are critical for today’s nanometer-scale ICs. The big challenge with ultra-shallow junctions is the boron implant. Boron is a small atom and is therefore easily accelerated in the beam that leads to a high projected range and straggle. To reduce this variability low energies are required, so beam deceleration is used. Another challenge is low beam current. The need for beam deceleration leads to beam blow up that requires a lower beam current. Lower energies also cause increased sputtering of the silicon surface. Lower energies also lead to increased backscattering of boron atoms. At 500 volts there is a 10% boron loss, and it increases to a 20% loss at 200 volts. Furthermore, these effects increase with accumulated dose. Finally, transient-enhanced diffusion creates problems where the silicon damage leads to increased movement of boron atoms.
The goal with ultra-shallow source drain regions is to create 50 to 100 nm deep junctions and 30 to 60 nm junctions for the extensions with minimal dopant redistribution and residual damage. One method to do this is to implant boron difluoride (BF2) instead of pure boron. This was a common technique in older processes and overcomes the deceleration problem, since the heavier molecule is not accelerated as much to begin with. However, the fluorine atoms contribute to boron sputtering.
This graph shows a retained boron dose versus a nominal boron dose in wafers implanted with either boron or BF2 at an equivalent boron depth. The trend lines are third order splinefits. For a nominal dose of one times ten to the fifteenth atoms per centimeter squared, the sputtering leads to a ten percent reduction in the retained dose for 500 volts or a twenty percent reduction at 2.2 keV BF2. Another solution is to improve boron transport efficiency by reducing beam blow up. One minimizes the beam path length to accomplish this. There is no deceleration post analysis as a result. Other approaches include electron confinement in the mass analysis magnet or using other beam focusing or shaping elements. A third approach is to use cluster boron beams; this topic is discussed in more detail on the Semitracks Online Training Website.
Most of us are familiar with the basic Coffin-Manson model, but there are actually several variations to this model that can be quite useful. Read on for more details.
The basic Coffin-Manson model is shown here:
where Nf is the number of cycles to fatigue, C0 is a constant, ΔT is the temperature cycling ranging, and c is the Coffin Manson exponent. There are several other forms of the equation that are used to model failures in semiconductor components and electronic systems. We’ll discuss these below.
Another version of the formula takes into account that there may be elastic as well as plastic deformation that occurs. Elastic deformation will not cause cracking; only plastic deformation does. Therefore, one should subtract the temperature range associated with elastic deformation out of the formula. One can modify the Coffin Manson model like this to take this into account:
where ΔT0 is the temperature range where elastic deformation occurs. The reason that one sees the main effect being low temperature is that ΔT - ΔT0 is greater in this scenario. For example, let’s assume that the elastic deformation region (ΔT0) extends 50°C below neutral stress at 150°C, or to 100°C. If we temperature cycle from -55°C to +125°C, then ΔT - ΔT0 is 155°. If we temperature cycle from 0°C to +125°C, then ΔT - ΔT0 is only 100°. Therefore the minimum temperature has the most impact. Absolute temperature swings will also factor in as well.
Another form of the Coffin-Manson model is the Norris-Landzberg Model. It is used for modeling cracking on solder materials. It is written like this:
The acceleration factor for the Norris-Landzberg model is given by:
The parameters for lead-tin solder are typically n = 1.9, m = 0.33, and Ea = 0.122eV. For lead-free solders, engineers typically use n = 2.65, m = 0.136, and Ea = 0.189eV.
Q: I have seen graphs (like I show in the graph below) where engineers have plotted median lifetime hours (log scale) as a function of temperature (linear scale), drawn a straight line through it, and then used the slope to determine the activation energy. Is this a correct way to calculate activation energy?
A: Normally, one would plot the temperature axis as one over T on a linear axis. By plotting T on a linear axis, you are not properly calculating the activation energy when drawing a straight line through the data.
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(Click on each item for details).
Copper Wire Bonding Technology and Challenges on May 7-8, 2012 (Mon.-Tues.) in Munich, Germany
Failure and Yield Analysis on May 7-10, 2012 (Mon.-Thurs.) in Munich, Germany
Semiconductor Reliability on May 14-16, 2012 (Mon.-Wed.) in Munich, Germany
Wafer Fab Processing on June 5, 2012 (Tues.) in San Jose, CA, USA
Reliability and Characterization Challenges on June 11, 2012 (Wed.) in San Francisco, CA, USA
Copper Wire Bonding Technology and Challenges on July 11-12, 2012 (Wed.-Thurs.) in San Francisco, CA, USA
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