This month we will begin a two-part series that provides an overview of chemical vapor deposition and the basic principles behind the technique. Process engineers usually refer to chemical vapor deposition by its short name CVD, so we will refer to it that way as well.
Probably the commonly used technique for deposition is chemical vapor deposition or CVD. CVD is a highly versatile method for depositing a wide variety of materials. It is a process that deposits a solid film on a heated substrate by reacting vapor-phase chemicals. One can use CVD to deposit epitaxial silicon, polysilicon, a variety of oxide layers, metal layers, barrier metals, and silicides.
Let’s describe the generic CVD process. The system introduces the reactant gases into the reaction chamber, and the gases diffuse through the boundary layer to the wafer surface. The reactants adsorb on the wafer surface. Once they do so, the reactants are now referred to as adatoms. The adatoms migrate to the growth sites, where they react and add to the film being formed. These reactions create a solid film and gaseous by-products, and these reactions may be the result of pyrolysis, reduction or oxidation. The gaseous by-products then desorb from the surface and diffuse through the boundary layer into the gas flow, where they are exhausted. The basic idea behind chemical vapor deposition is rather simple: we react chemicals on the surface to grow a desired layer. For the purposes of this discussion let’s assume the CVD chemicals we are considering are gases are gases. Of course, there are many complicating details. These include the gas transport to the wafer surface, the gas phase reactions, the gas adsorption onto the surface, the mobilities of the precursors used on the surface, the reaction of the precursors, whether they be surface or gas-phase reactions, the reaction byproducts, the byproduct desorption, and the byproduct transport away from the wafer surface. Each of these can affect the growth rate, the uniformity and the purity of the deposited layer.
As thin films grow, they follow the Gibbs free energy principle. The free energy rule states that the total free energy of a system decreases with increasing size of particles. This leads to the growth pattern described above. First, particles nucleate. Next, the individual nuclei grow. As they increase in size, the individual nuclei begin to impinge on each other. The overall system lowers the free energy through coalescence. As growth continues, the remaining area forms channels, which slowly fill in, leaving holes, which are the last to close up.
In chemical vapor deposition there are two types of reactions: heterogeneous and homogeneous. In a heterogeneous reaction, the reaction occurs on or very close to the wafer surface. This is preferred since the reactions occur selectively on the heated surfaces. In a homogeneous reaction, the reaction occurs in the gas phase. This is undesirable since it results in sold particles of material falling down onto the film.
The best way to model the CVD process is through the Deal-Grove Model. This model is named after Andrew Grove, the famous leader of Intel, and Bruce Deal, a research colleague of his, and has been around since the late 1960s. Before we show the equations, we need a few basic terms and assumptions. The five steps of the CVD process we mentioned two slides back can be grouped as gas phase and surface processes. In each group, one step will be the rate-limiting step. Grove described these processes in terms of flux F, where flux units are atoms per square centimeter second. This term is used both for transport and reaction flux.
The Deal-Grove model is also used for oxidation, but we will show how it is used to model the CVD reaction process. The concentration distribution of the reactant gas and the flux from the bulk of the gas to the surface is given by F1. F2 corresponds to the flux or the consumption of the reactant gas. In this model, F1 is equal to the gas phase mass transfer coefficient times the difference between the reactant concentration in the gas (CG) and the reactant concentration at the surface (CS).
The Deal-Grove model leads to two film growth regimes, a mass transport-limited regime and a surface reaction rate-limited regime. The mass transport-limited regime dominates at higher temperatures, and the growth rate is only a weak function of temperature. In this regime, the reaction rate is fast enough to use all of the incoming and available reactants, so the flux of the reactants is the key process control parameter. The surface reaction rate-limited regime dominates at lower temperatures. Here the growth rate is a strong function of temperature, since the reaction rate is governed by temperature.
Next month we will cover the second part of chemical vapor deposition.
A parameter associated with snapback is Injection Induced Breakdown Voltage, or BVii. BVii is a good monitor parameter for snapback, since it encompasses the effects of the current gain of the parasitic bipolar transistor, the avalanche multiplication factor, and the effective substrate resistance. Changes to these three values will affect BVii, and therefore give an indication of a transistor’s susceptibility to snapback. One of the challenges with BVii is the gate voltage at which one should take the measurement. Historically, measuring BVii at VG = 0.5*VD worked well, since snapback tends to occur in the saturation condition. With smaller feature sizes, that may change as the maximum in hot carrier injection moves more toward VG = VD. This graph shows an example of both a good (green) snapback curve, and a poor (red) snapback curve. We also point out where BVii lies on the plot.
A good paper to read concerning process effects on BVii is "ESD-related Process Effects in Mixed-voltage Sub-0.5mm Technologies" by Vikas Gupta, Ajith Amerasekera, Sridhar Ramaswamy, and Alwin Tsao. You can find this paper in the 1998 EOS-ESD Symposium Proceedings.
Please visit http://www.semitracks.com/courses/analysis/failure-and-yield-analysis.php to learn more about this exciting course!
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Advanced Thermal Management and Packaging Materials on April 22-23, 2013 (Mon.-Tues.) in Philadelphia, PA, USA
Semiconductor Reliability on May 6-8, 2013 (Mon.-Wed.) in Munich, Germany
Copper Wire Bonding Technology and Challenges on May 13-14, 2013 (Mon.-Tues.) in Munich, Germany
Failure and Yield Analysis on May 13-16, 2013 (Mon.-Thurs.) in Munich, Germany
MEMS Technology on May 15-16, 2013 (Wed.-Thurs.) in Munich, Germany
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