This month, we continue our look into bump processes. Let’s look at fine or tight pitch issues a little further. Notice that if we have an 80µm pitch pad structure and use an 85µm height solder bump we can have problems with shorting between bumps. We can eliminate this problem by going to a 40µm solder bump, but this introduces other problems. For example, a small bump will be more susceptible to electromigration. The shorter height may also introduce manufacturing problems, like flowing underfill around the solder bumps efficiently. This is where the copper pillar can be advantageous. We can easily achieve an 80µm pitch and an 85µm height because of the pillar shape and eliminate wetting to the sidewalls, which might increase the pillar width.
For copper pillar bumping, we can use the same two approaches: solder masked defined and pad defined. In the solder mask defined approach, we deposit solder in the openings in the solder mask, bring the chip with its copper pillars in contact to the solder, and then reflow the solder to make the connection. In the pad-defined process, we deposit solder on the copper pillar, bring the chip in contact to the bare copper pad, and then reflow the solder. This creates the connection between the chip and the substrate.
This series of diagrams in Figure 2 help to describe the copper pillar bump process flow. After wafer cleaning, one sputters titanium and then copper on top of the chip and patterns these materials such that they only remain on the pads. After etching the Under Bump Metallization (UBM) metals and removing the resist, one can then expose and develop an area above the bond pads and then electro-deposit a copper layer that forms the pillar, followed by solder. Once the solder is deposited, one can remove the resist and reflow the solder to create the solder bump on top of the pillar.
Figure 3 shows the equipment used for ball attach reflow and wash. This is a typical in-line process for Ball Grid Array packages.
One method for creating solder balls is to use a screen print process. The engineers use a stencil and substrate to create the solder balls and simultaneously align them to the package and board. The Flux/Paste is for the balls; the flux dissolves the native oxides on the balls, permitting wetting. The stencil can then be used with the ball mounter head. It is attached to the ball mounter head. The ball mounter head is a vacuum chuck that picks up the balls from the ball reservoir, aligning them to the stencil. During the attachment step one releases the vacuum to let the balls stick in the flux.
To improve bonding, it can be helpful to build up structure on the bond pad like a noble metal bond pad cap. This helps prevent oxidation and diffusion of other materials. BOAC is one such technology; it uses a copper nickel palladium gold structure that resists intermetallics. It works well for high temperatures. Some companies use deposited copper or thick metal copper layer with a nickel-palladium capping layer.
Next month in Part III we will discuss redistribution layers and the methods for creating these layers.
After initial packing, the reels, tubes, and trays are usually then packed into boxes for shipping. Most large semiconductor manufacturers use distribution centers located in or near major worldwide shipping hubs. Most components are also small enough that they can be shipped by air via UPS, FedEx, DHL, or other couriers. One concern with shipping components is that components are generally static sensitive, and the shipping process does not allow for static control. In order to protect the components, engineers will use static protective bags, tubes and reels. Furthermore, they use labels to indicate that the components being transported are static sensitive. The semiconductor industry uses labels like the ones we show on the right to indicate static sensitivity. The military requires labels, and JEDEC-compliancy requires the labels as well. One must put labels on the unit pack and the intermediate and exterior containers.
Components also need to be labeled as to their moisture sensitivity. The moisture that is being absorbed by the device is inherent during the assembly and molding process and this moisture trapped within the device may cause the unit to crack, known as the popcorn effect, during IR reflow, vapor phase reflow, or similar processes at board mounting operation due to the high amount of heat that is being applied. The bake step we mentioned removes this trapped moisture inside the package at a slower pace without causing any package cracking or solderability concerns. The units can then be dry packed afterwards to ensure no moisture absorption will take place until the devices are ready to be mounted to the boards by our customers. Operators then list the MSL sensitivity on the labels on the exterior of the box and dry-ship bags.
Please visit http://www.semitracks.com/courses/reliability/product-qualification.php to learn more about this exciting course!
(Click on each item for details).
Failure and Yield Analysis on May 5-8, 2014 (Mon.-Thurs.) in Munich, Germany
MEMS Technology on May 12-13, 2014 (Mon.-Tues.) in Munich, Germany
Semiconductor Reliability on May 12-14, 2014 (Mon.-Wed.) in Munich, Germany
Product Qualification on May 15-16, 2014 (Thurs.-Fri.) in Munich, Germany
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