Let’s summarize some of the more important second-order effects. For dry oxidation and ultrathin oxides, the Deal-Grove model will significantly underestimate the oxide thickness when it is less than 30 nanometers. Some process engineers will adjust tau to improve the fit, but that is a less than satisfactory answer. Another approach is to use a more sophisticated model. For example, the Massoud model adds an additional term to handle the thin oxide problem. Dopants affect the oxidation process as well. The presence of dopants in the silicon will enhance the oxidation rates. However, there are different mechanisms for different dopant species. For instance, boron mainly affects the diffusion limited growth regime. The pile up in the oxide weakens the oxide structure, enhancing the diffusion of the oxidizing species. Phosphorus mainly affects the oxidation rate limited regime. Researchers believe this may be related to the concentration of silicon vacancies at the surface.
Crystal orientation also affects the oxidation rate. The oxidation rate is higher for the <111> (pronounced “one-one-one”) surface than the <100> (pronounced “one-zero-zero”) surface. This mainly affects the oxidation rate limited regime, and researchers believe the effect is due to a higher density of exposed silicon atoms.
There are four types of charge that can affect the behavior of a transistor or parasitic device. They are mobile ion charge, oxide trapped charge, fixed oxide charge, and interface trapped charge. Fixed oxide charge manifests itself as a sheet of positive charge located within 2 nanometers of the silicon-silicon dioxide interface. It is attributable to incompletely oxidized silicon atoms that have a net positive charge. The charge always remains positive. This charge can be an artifact of the termination of the oxide/annealing cycles, so the best method for reducing this effect is optimizing the oxidation/annealing cycles. Mobile ion charge, usually a positive ion like sodium or potassium in parts per million concentrations can cause measurable instabilities in transistors. It becomes mobile at higher temperatures and in the presence of an electric field. Even parts per million level concentrations can cause measurable instabilities. Process engineers reduce this problem through cleanliness in manufacturing and other methods like gettering and silicon nitride barriers.
Interface trapped charge is also due to incompletely oxidized silicon. The incompletely oxidized silicon produces a dangling bond. It tends to be very close to the interface. The charge may be positive or negative and may change during device operation. Engineers express this interface trapped charge as Dit (pronounced “D-sub-I-T”), or a density per unit energy. Oxide trapped charge occurs when silicon-oxygen bonds are broken due to ionizing radiation, or through exposure to energetic particles during processing, such as plasma etching or ion implantation. This can lead to electrons or holes trapped at defects in the bulk oxide. These bonds can normally be repaired by annealing.
This diagram shows the four different types of charge that can occur in the silicon dioxide and at the silicon/silicon dioxide interface. Mobile ions such as sodium and potassium can be found scattered throughout the silicon dioxide layer. In the presence of an electric field however, they can be attracted to the interface. Oxide trapped charge is found randomly throughout the oxide. If there is an excess of either positive or negative fixed charge, it can affect device operation. Fixed oxide charge tends to occur in the transition region between the silicon and the silicon dioxide. Finally, interface trapped charge occurs right at the silicon/silicon dioxide interface.
In conclusion, we delved into thermal oxidation in more detail. We described the Deal-Grove model constants in more detail and discussed their impacts on the oxidation process. We also discussed second-order effects to the oxidation process. This includes items like dopants and dopant concentrations, the crystal orientation of the underlying silicon, the pressure of the gases used in the process, and any pre-treatment effects. While the Deal-Grove model provides good insight into the basic oxidation process, more accurate modeling that is required for today’s nanometer scale devices requires that one understand and account for second-order effects. This means that more sophisticated models might be required.
A number of instruments in the semiconductor industry use mass spectrometers. Engineers and scientists use them for a range of activities, from monitoring gases to understanding the doping profile in a semiconductor material, a technique known as Secondary Ion Mass Spectroscopy (SIMS). Let’s talk about one of the more common types of mass spectrometers used for SIMS in more detail.
Currently, the more common type of mass spectrometer used in SIMS is the sector field mass spectrometer. This uses an electrostatic sector analyzer coupled with a magnetic sector analyzer. This concept uses the Lorenz force to bend the ion through the electrostatic and magnetic sectors. The Lorenz force is equal to the Centripetal force, which is given by the equation below.
The mass-to-charge ratio can be calculated from the induced radius of curvature, or bend R sub E through the electrostatic analyzer, and the bend R sub M through the magnetic sector analyzer, as we show here.
One can use an energy-resolving slit to filter out the unwanted ions from the analysis process, because the unwanted ions will be bent to a different degree. Other types of analyzers include the quadrupole mass analyzer, which separates masses by resonant electric fields, and the time-of-flight mass analyzer, which calculates mass based on the time required to traverse a known distance after a given acceleration.
Q: I heard the term flying probe tester recently. What does that mean exactly?
A: Flying probe testers is a term used to contrast against bed-of-nails testers. In a flying probe test system, an on-board computer places the needles or probes over the appropriate locations on a Printed Circuit Board to make electrical contact. This allows better utilization of the tester resources, since one only sets down on pads of interest. It also removes the need for fixturing. In a bed-of-nails tester, the probe points are fixed, so one would need a fixture to probe on a particular package type as an example.
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