Education and Training for the Electronics Industry
Semitracks provides education, training, and certification services and products for the electronics industry. We specialize in serving Semiconductor, Microsystems and Nanotechnology suppliers and users. Semitracks, Inc. helps engineers, technicians, scientists, and management understand these dynamic fields. We offer courses in Semiconductor Reliability, Test, Packaging, Process Integration, Failure and Yield Analysis, and Focused Ion Beam technology. Learn from the Experts.
As the semiconductor industry approaches the point where High-K dielectrics will be necessary, a number of challenges will occur. One problem is the performance of the gate connection. It will be necessary to use a metal or metal-like gate material in order to achieve the necessary performance. Traditional heavily-doped polysilicon will not provide the control and performance necessary. Currently, the leading approach to fabricating a metal gate is called FUSI (pronounced "foo-see," short for fully silicided gate), which is basically an extension of existing processes. Silicides are already used on top of the source, drain, and gate to improve resistance and provide a better interface between the silicon. Silicides are formed by depositing a metal, such as titanium, nickel or cobalt, on top of the silicon, followed by a thermal step (usually rapid thermal processing) to create a silicide, such as TiSi2, CoSi2, or NiSi. In the FUSI approach, this step is simply continued until all of the gate silicon is converted to a silicide. There are two approaches to metal gates: depositing the metal gate first, or depositing the metal gate last. FUSI falls into the second category. At this time, there is not a preferred approach, although engineers are working to make the thermal processing temperatures as low as possible. The winner is likely to exhibit the best combination of device performance, reliability, and simplicity in processing.
Semitracks' new and improved Online Training is convenient, up-to-date, and cost effective. Access the same material presented in our courses whenever you need it, right when you need it without having to worry about the high costs and hassle of traveling. The semiconductor field is an ever-changing one. With access to the most current information, you can stay on top of the new technology. Online Training is also very cost effective. For only $500 per year, you gain access to thousands of dollars worth of courses and course material.
Give our Online Training a try – for free. This month's topic is Micro BGA: Lead Frame Preparation.
This segment is no longer available. If this topic interests you, perhaps you would be interested in our Online Training. For more information or to sign up, please visit http://www.semitracks.com/online-training/.
International Symposium for Testing and Failure Analysis
November 12-16, 2006 at the Renaissance Austin Hotel in Austin, TX, USA
Semitracks, Inc. and Semiconductor International have put together a course which will provide an overview of the current business climate, anticipated trends and the associated impact on assembly/packaging roadmaps. There will be an in depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution.
Packaging Technology and Challenges on September 11-12, 2006 in Dallas, TX, USA
Invest in yourself and your staff. Time is running short to enroll in our Summer courses on Packing Technology, Packaging Design, Process Integration, Reliability, and Failure and Yield Analysis. Come and learn from the experts!
Semiconductor Process Integration
Semitracks, along with Semiconductor International, have put together a 2-day course on Semiconductor Process Integration for CMOS and BiCMOS Technologies. Dr. Badih El-Kareh of Texas Instruments will give an overview of the process integration challenges associated with today's advanced semiconductor devices. Dr. El-Kareh will cover passive and active components, contact and interconnect issues, isolation technologies such as STI and SOI, transistor integration issues, as well as full CMOS, BiCMOS and High-Speed Bipolar Process Integration techniques.
Process Integration on September 12-13, 2006 in Dallas, TX, USA
Packaging Design and Modeling
Semitracks, Inc. and Semiconductor International have assembled a course on IC Packaging Design and Modeling. This course provides an overview of the packaging design process. The course covers current packaging technologies, including chip scale packaging, Ball Grid Array technology and other current concepts. This class focuses on techniques and the importance of thermal and mechanical simulations. Discussions and examples will concentrate on thermal performance simulations, assembly & packaging stresses, package reliability (including solder joint fatigue simulation), and interactions between chip and package. In addition, a special section will be examples of successful wafer level simulations.
Packaging Design and Modeling on September 13-15, 2006 in Dallas, TX, USA
Failure and Yield Analysis
Failure and Yield Analysis is an increasingly difficult and complex process; engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. This is a multi-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure.
Failure and Yield Analysis on September 18-21, 2006 in Boston, MA, USA
Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. Analysis and experimentation is now performed at the wafer level instead of the packaging level. This requires knowledge of subjects like: design of experiments, testing, technology, processing, materials science, chemistry, and customer expectations. While reliability levels are at an all-time high level in the industry, rapid changes may quickly cause reliability to deteriorate. Your industry needs competent engineers and scientists to help solve these problems.
Semiconductor Reliability on September 25-27, 2006 in Boston, MA, USA
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