In this month’s newsletter, we’ll be discussing Thermal Processing. There are four main thermal processes: thermal oxidation, thermal annealing, thermal diffusion, and thermal nitridation. With thermal oxidation, engineers react silicon with oxygen to grow a thin film of high quality thermal oxide. This is one of two common methods for creating silicon dioxide; the other is the use of chemical vapor deposition to deposit the layer. With thermal annealing, engineers use heat to activate dopants and repair silicon lattice damage from ion implantation. They also use annealing to form silicide layers, like titanium, cobalt, or nickel silicides by reacting the metal with the silicon surface. They also can use annealing to densify oxides like those deposited by chemical vapor deposition. With thermal diffusion, engineers can redistribute implanted dopants in the silicon. And finally, with thermal nitridation, engineers can react silicon with oxygen and a nitrogen-containing gas like nitrous oxide or nitric oxide to grow a nitrided dielectric like silicon oxynitride.
Other thermal processes include chemical predeposition and chemical vapor deposition. Historically, engineers used chemical predeposition as a method of doping prior to the development of ion implantation. One would deposit a dopant-containing material, known as a precursor, on a heated wafer surface. Precursors can be solids, liquids, or gases. Engineers control the amount of dopant introduced into the Si by two factors: the solid solubility of the dopant and the diffusivity of the dopant. Both factors are a strong function of temperature. Although chemical predeposition is no longer used in mainstream integrated circuit processing, it is still used in some specialized applications like compound semiconductor processing and new applications like silicon nanoparticle formation. Another more common thermal process is Chemical Vapor Deposition, or CVD. It is not a conventional thermal process, but it does occur at relatively high temperatures. We discuss CVD in more detail elsewhere in this system.
Let’s make a few comments on thermal budgets. This is the upper limit to the amount of heat and time the process can endure without creating harmful side effects. One of the biggest problems with thermal processing is that it not only moves atoms that one wants to move, but it also moves atoms one would prefer not to move. For example, a silicide step that uses high temperatures might cause the source-drain implants to move further. This means that engineers need to be careful about how they construct the process in order to limit these effects. This phenomenon led scientists to come up with the term “thermal budget.” We measure the total amount of thermal energy received by the wafer during thermal processing, and then work to stay below this number. As process nodes shrink, the thermal budget also shrinks, making this task quite difficult today. It is something all scientists and engineers need to characterize and study for their processes.
One of the more important thermal processes is thermal oxidation. Engineers use silicon dioxide, both thermal and CVD, for several uses. The first one is as a surface dielectric. We use surface dielectrics to isolate devices from one another like transistors, capacitors, and interconnect. Device manufacturers sometimes isolate transistors using LOCOS (pronounced “low-cos”) field oxide. They also isolate inter-metal dielectric, or IMD, with oxide as well, although this oxide is normally a deposited oxide.
The second use is as a device dielectric. Process engineers use this dielectric within a device to actively control the device operation. For example the gate oxide controls the MOS (pronounced “M-O-S”) transistor threshold voltage and drive current, and the capacitor oxide controls capacitance, like one might use for DRAM (pronounced “D-ram”) cells.
The third use is as a mask. Engineers do this for ion implantation, where the oxide protects underlying film from being doped, and for etching, where the oxide protects the underlying film from being etched, like a sidewall spacer oxide.
The fourth process application for an oxide layer is the etch stop. This allows complete etching of an uncovered area while preventing etching of the underlying film in the covered area.
The fifth application is surface passivation. A surface passivation reduces the reactivity of silicon surface and protects against contamination. This is a common final layer on semiconductor devices to provide protection in the package.
The sixth and final application is as a buffer layer. A buffer layer prevents film peeling when two films have very different coefficients of thermal expansion. A common use of the buffer layer is the pad oxide between the silicon nitride mask layer and the silicon surface. This pad oxide helps prevent damage to the silicon during subsequent thermal processing, which leads to stacking faults and other crystalline damage in the silicon.
This table summarizes some of the more important process applications for silicon dioxide. As you can see, silicon dioxide can be used for a wide range of applications within a semiconductor device, ranging from gate oxides, to re-oxidation steps, to sacrificial layers to enable defect-free processes subsequent to the step.
Most of us usually learn about diffusion in college in terms of their mathematical equations. However, visualizing diffusion can make it much easier to understand. This series of images can help us visualize the concept. Let’s assume we have a hypothetical situation where we have a number of charge carriers in a box like we show here.
These carriers will move around within the box, and the speed of their movement will be governed by the temperature of the system. The lower the temperature, the slower the carriers move; the higher the temperature, the faster the carriers move. Notice that we have a lot of carriers on the left, and no carriers on the right.
Now, let’s remove the wall. Since the carriers move randomly, about half are moving to the left and half are moving to the right at any given point in time. Those near the boundary can now move across the boundary. Because the barrier is now missing, there is a net movement to the right, because those right on the boundary have a 50% chance of moving to the right, and a 50% chance of moving back to the left. Fick’s Laws are the equations that govern this motion.
In general then, we have this random motion that results in a definite and predictable motion of the entire population of the carriers, and we call this Gaussian or Fickian diffusion. Like the movement of carriers, diffusion slows down with temperature, and with state changes from liquid to solid, but it still occurs, even at very low temperatures. Not only does this occur in semiconductor materials, but it is also associated with other mechanisms, like intermetallic growth. For instance, Kirkendall voiding with intermetallic growth as an example of this, since diffusion of gold into aluminum occurs more quickly than diffusion of aluminum into gold.
Q: What is the p-value term in an ANOVA (Analysis of Variance) calculation?
A: The P value tests the null hypothesis that data from all groups are drawn from populations with identical means. Therefore, the P value answers this question: If all the populations really have the same mean, what is the chance that random sampling would result in means as far apart as observed in this experiment?
If the overall P value is large, the data do not give you any reason to conclude that the means differ. Even if the population means were equal, you would not be surprised to find sample means this far apart just by chance. This is not the same as saying that the true means are the same. You just don't have compelling evidence that they differ.
If the overall P value is small, then it is unlikely that the differences you observed are due to random sampling. You can reject the idea that all the populations have identical means. This doesn't mean that every mean differs from every other mean, only that at least one differs from the rest.
Please visit http://www.semitracks.com/courses/analysis/eos-esd-and-how-to-differentiate.php to learn more about this exciting course!
(Click on each item for details).
Semiconductor Reliability on September 3-5, 2014 (Wed.-Fri.) in San Jose, CA, USA
Failure and Yield Analysis on September 8-11, 2014 (Mon.-Thurs.) in San Jose, CA, USA
Product Qualification on January 26-27, 2015 (Mon.-Tues.) in San Jose, CA, USA
Wafer Fab Processing on January 26-29, 2015 (Mon.-Thurs.) in San Jose, CA, USA
EOS, ESD and How to Differentiate on January 28-29, 2015 (Wed.-Thurs.) in San Jose, CA, USA
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at firstname.lastname@example.org.
To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (email@example.com).
We are always looking for ways to enhance our courses and educational materials.