In this section we will cover substrate materials. These are the materials used to create interposers and other substrates used in microelectronics packaging.
Let's begin with some terms and definitions. Engineers and scientists in the semiconductor industry use the term interposer to describe a substrate that goes in between the die and the printed circuit board. It is used to route and re-distribute signals to a different and/or larger footprint. We use the term BU or build-up to refer to the layers--both conducting and insulating--that create the interconnect between the die and the printed circuit board. These layers are typically built upon a core substrate material. We use the term thermoset to refer to an epoxy system that cures by the application of heat. Also importantly, once the thermoset is cured the process cannot be reversed; it is “set.”
Many printed circuit boards and substrates in use today are composed of a material called FR4. The FR in FR4 stands for fire retardant. The 4 in FR4 is a particular composition that is a glass fiber epoxy laminate. 1.60mm FR4 uses 8 layers of (7628) glass fiber material. 7628 is a common glass fabric that has a particular weight, thickness, warp and weft. The red UL/manufacturers logo is in the middle (layer 4). FR3 is mainly a European product. It is basically FR2, but instead of phenolic resin it uses an epoxy resin as binder. The basic layer is paper. FR2 is a paper material with phenolic binder. It is UL94-V0. FR1 is basically the same as FR2, but it has a higher glass transition temperature of 130°C instead of 105°C for FR2. Some laminate manufacturers that produce FR1 will not produce FR2, since the costs and usages are similar and there is no advantage to making both.
CEM stands for composite epoxy material. CEM-1 is a paper based laminate with one layer of (7628) woven glass fabric. It is not suitable for creating plated through holes. CEM-3 is very similar to FR4. Instead of woven glass fabric a 'flies' type is used. CEM-3 has a milky white color and is very smooth. It is a complete replacement for FR4 and has a very large market share in Japan. A 'prepreg' is an epoxy coated glass fabric. It has two usages: as a dielectric layer in multilayer PCBs, and as the raw material for FR4. 8 layers of '7628' prepregs are used in one sheet of 1.60mm FR4. The central layer (no. 4) usually carries the red company/UL logo. Plated through holes--or PTH--provide electrical connection from one side of the board to another, or from one layer within the board to another. Plated through holes can be made on FR4 and CEM-3 boards, but not on the other types. Finally, the term IPN --or Interpenetrating Polymer Network--is a term used for a polymer comprising of two or more networks, which are at least partially interlaced on a polymer scale.
Here are the physical properties of some of the more common printed circuit board materials. We compare dielectric constants, surface resistance, volume resistance, glass transition temperature arc resistance, flexural strength lengthwise, flexural strength crosswise, coefficients of thermal expansion and suitability for plated through holes. Notice that FR4 has a relatively high glass transition temperature, a superior arc resistance, and high flexural strength, both lengthwise and crosswise. Another advantage to FR4 is that it is a suitable material for plated through holes.
Here is an example of a board manufactured from FR4. Untreated FR4 is usually transparent. The green color comes from the solder mask in the PCB finished product. Here we have increased the magnification on a portion of the board. Notice that the solder traces are visible, along with the plated through holes. The white lettering and outlines are added to help with placement of components during the board assembly process.
This is a cross section example of a multi-layer board with core resin and build up layers. The interconnection occurs through plated through holes and vias. The key defects due to processing and intrinsic CTE mismatches between various components or materials issues are: cracks through dielectric layers, cracks through plated through holes, delamination of vias, delamination at metal/dielectric interfaces, and defects in the dielectrics.
This figure shows some of the typical substrate failures that can occur with a substrate that contains a core structure, plated-through-holes and build-up materials. These failures include mechanisms seen in highly accelerated stress testing (HAST) such as: lead migration over or under the solder resist at the interface, copper migration in cracks in the dielectric, and via delamination. Other types of failures seen in temperature cycling include: copper line cracks due to dielectric cracking, barrel cracking, via delamination, and polymer cracks.
There are several steps to creating a successful process for decapsulating an IC. Barry and Nancy Weavers of Left Coast Instruments put together a checklist of 8 steps to help you accomplish this task. We summarize the steps below.
First, determine the acid type:
90% Fuming Nitric Acid (HNO3) is the least expensive, and is the lowest grade that will decapsulate plastic packages.
98% Fuming Nitric Acid (HNO3) produces a faster etch rate, with much less metal damage. It can also be used over a wider temperature range.
Red Fuming Nitric Acid (HNO3) can be used with some systems, like the Elite Etch.
96 to 98% Sulfuric Acid (H2SO4) is the least expensive, and is the lowest grade that will decapsulate high-temperature packages.
20% Fuming Sulfuric Acid (H2SO4) produces a faster etch rate, with much less metal damage.
Next, determine the etch temperature:
Failure analysts typically use HNO3 in the 75 to 80°C range, mixed acids in the 80 to 90°C range, and H2SO4 in the 220 to 250°C range. In packages where unpassivated metals are used, a different technique is required. A mix of 3:1 is commonly used. The temperature range should be between 30 and 50°C in order to protect the metallization. The etch rate will be much slower, but the metal will be better preserved.
Next, determine the heat up time:
Programming the heat-up time depends on the mass of the device. Start with the maximum heat-up time. Drop the time in 5-second increments until the etched hole is reduced in size. Add 5 seconds to the reduced heat-up time for the correct heat-up time.
Next, determine the etch volume:
The etch volume is the amount of acid used (ml/min) that is programmed in the etch time. As a general rule, when using nitric acid one should start with a volume of 3 ml/min. The color of the waste material will determine the correct volume. If the waste acid is light brown to clear the volume is too high. If it is dark brown and not moving freely the volume is too low. If the waste acid is brown and moving freely the volume is correct.
Next, determine the correct fixturing:
Once the above have been determined, the correct ﬁxturing can be chosen. The acid type used for decapsulation determines the deﬁnition gasket.
Next, determine the etch time:
The etch time is the amount of time (in seconds) that the device is actually being etched. The easiest way to determine the etch time is to run a sample of the package for a short period of time. For SO and TSOP packages start with 10 seconds; for all other packages 60 seconds works well as a starting time - these are your base etch times.
Next, choose Pulse or Reciprocal Etch mode:
The choice of pulse or reciprocal etch mode determines the relative angle of the sidewall. A reciprocating etch will produce a relatively straight sidewall, while pulse etch will produce a more rounded sidewall.
Finally, determine the rinse time:
The rinse time serves two functions. The ﬁrst is to clean the part with cold acid and ﬂush the part and waste line before nitrogen ﬂush. The second, and very important function, is to make very small changes to the etch cavity. Start with “No Rinse” and then adjust as required.
If you follow these steps, you should be able to achieve good, repeatable results, like we show in the image below.
Q: I analyzed a customer return failure and the failure mechanism appears to be voiding due to intermetallic growth. What do you think happened to this part?
A: Based on the evidence, the part you're analyzing saw high temperatures for an extended period of time. We can't tell from the images when that might have happened though. It could have occurred during bonding (not likely, but possible), during some other portion of the assembly operation (also not likely, as you would have had many other failures), or during field use (more likely). You'll need to work with your customer to track down the root cause. Are other bond pads on this chip showing the same voiding?
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