This year’s International Electron Device Meeting (IEDM) discussed a wide range of approaches for creating CMOS transistors with better performance. One axis of performance that is important is higher speed for faster switching. Higher speed invariably means higher mobility, so researchers have been investigating techniques to make this happen.
Silicon has a moderate mobility, but there are methods to improve it marginally. This can be done using strain. Companies like Intel and TSMC offer technologies and devices that use strained silicon. To get a larger improvement, one needs to consider alternate materials.
This table shows the major materials and candidates that can be or are used in CMOS devices. Silicon is the existing material for most devices. The electron and hole mobility for silicon are reasonable, but they’re not the highest numbers that are potentially available. Germanium has a much higher electron mobility and a lower electron mass. More importantly, germanium has the highest hole mobility of any of the major semiconductor materials at 1900 cm2/V-sec. It also has the lowest mass for heavy holes, which is the main type of carrier in a p-channel transistor. Some companies, like IBM, mix Si and Ge together in the transistor channel to improve mobility. GaAs, InP, InAs, and InSb all have even higher mobilities. InAs and InSb have the highest mobilities, but the bandgaps for these materials are quite low. GaAs and InP have a larger bandgap, which makes them more useful in low power applications.
Stay tuned for the conclusion of this article in January!
Energy/Band Structure Diagrams seem arcane, something that one learns for their college device physics course and then forgets. However, there is a lot of useful information in the diagram. Band structure diagrams measure energy as a function of wave vector. The wave vector is best understood by looking at the crystal structure. This figure shows a portion of the crystal structure for diamond and zincblende lattice structures. The center point of the crystal is given by gamma (Γ) and the faces of the crystal are given by X and L respectively. The X faces represent the intersections of the crystal lattice with the box (the [100] axis), and the L faces represent the intersections of the remaining faces of the crystal (the [111] axis). This structure is known as the Brillouin zone.
The figure on the right shows the energy band structure for silicon. The red lines show the energy lines as a function of k- space or wave vector. The red lines above the bandgap denote the conduction bands, and the lines below indicate the valence bands. The distance between the lowest energy in the conduction band and the maximum energy in the valence band represents the band gap energy. For silicon, it is 1.11eV. Notice that the minimum in the conduction band does not line up with the maximum in the valence band. This is because silicon is an indirect band gap material. If the minimum and maximum line up in k-space, the material is a direct band gap material. The shape of the bands relates to the mobility of the semiconductor. If the valence band has a sharp bend near the maximum point, then the mobility will be high for holes. If the conduction band has a sharp bend near minimum point, the electron mobility will be high. The outer valence band indicates the energy structure for heavy holes, while the inner valence band indicates the energy structure for light holes. Some energy diagrams show structure at higher energies (+3eV and higher) and lower energies (-3eV and lower). This structure is not as important for semiconductor operation as very few electrons and holes operate in these regions.
Q: How do I keep from losing a very small die when I decapsulate it with sulfuric acid?
A: Probably the best way to keep from losing a very small die is to put the package in a fine wire mesh bag and dip the bag in the sulfuric acid. That way, the die and lead frame stay contained. You can then dip the bag in isopropyl alcohol to stop the etch, rinse the bag in deionized water, and retrieve the die and lead frame under a low power microscope.
(Click on each item for details).
Semiconductor Reliability on January 17-19, 2012 in San Jose, CA, USA
Wafer Fab Processing on January 17-20, 2012 in San Jose, CA, USA
Introduction to Polymers and FTIR on January 17-18, 2012 in Phoenix, AZ, USA
Photovoltaics Technology and Manufacturing on January 18, 2012 in Toronto, Canada
Failure and Yield Analysis on January 23-26, 2012 in Cambridge, United Kingdom
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