This article is a continuation of last month’s article. As we discussed last month, sometimes failure analysts can best understand the FA procedure for a component by thinking about the process in terms of the type of failure. This is a flowchart that describes how to analyze a scan-based failure at the wafer level.
We begin with the Automatic Test Pattern Generation (ATPG) Diagnosis data. This information comes from EDA tools like TetraMax™ from Synopsys, Encounter Test™ from Cadence, or Mentor Graphics’ tool Tessent™. Test engineers will sometimes run these routines on failures to help with the diagnosis process. If this data is not available, one should request it from the customer. Without this information, it can be quite difficult to troubleshoot a scan-based failure. Today’s complex components practically require this approach to the analysis. Without assistance from the electrical test data, the analyst must resort to hunting for what amounts to a needle in a haystack. Each year, the needles get smaller and the haystack gets larger!
If we have the data, or once we have the data, we can analyze the failing candidate nodes to see if there is top-level metal access. We can examine the GDSII files for this information. The higher in the metal stack the defective candidate appears, the less parallel polishing we need to perform to access the layer. Once we have identified candidate locations to examine, we can mark the locations on the die with a focused ion beam or laser system. This point in the analysis also provides a good opportunity to examine the sort data, inline data, and other data items for clues as to where the failure might be occurring and why. Next we remove the overlying layers to expose the metal layer of interest. Ideally, this metal layer is the uppermost layer in the defective node. With this metal layer exposed, we can perform passive voltage contrast. Passive voltage contrast can be used to identify opens and shorts. If we don’t see incorrect contrast, then we can remove the chip layers down to the next metal layer in the node, or down to the upper-most metal layer in the next candidate. We would continue this process down through the backend of the process, or through the interconnect and dielectric layers. Once we see incorrect contrast or the defect itself, we can determine if we need further analysis. This might involve a cross-section or TEM liftout. We can then examine the defect with the SEM or TEM as appropriate. If we do not see the defect after removing all of the interconnect and dielectric layers, we can decorate the substrate to highlight potential defects in the silicon. At this point, we can write up our findings in a failure analysis report.
The flow shown in the gold flowchart shapes assumes that we do not have electrical access to the die for testing in conjunction with failure analysis techniques. If we were to have access to wafer-level test with failure analysis lab tools, then it may make sense to perform the analysis from the backside. We show this alternate flow in the blue-gray color. We can thin the sample to around 100µm to provide better transmission of the laser signals and light emission. Once we have the sample thinned, we can use techniques like Light Emission and Laser Voltage Imaging to provide additional diagnosis capability. After the Laser Voltage Imaging Analysis, we will need to return to the main flow to expose the defect. Depending on the results of the LVI and Light Emission analysis, we may have identified a metal interconnect segment, via, contact, or transistor to examine further. This might mean we return to the main flow at a different point than shown here in the flowchart.
Although flowcharts provide only a moderate degree of help for specific analysis cases, they do provide a high-level overview of the process. One can construct more specific flowcharts that account for the equipment available for analysis, the circuits to be analyzed, and the importance level of the analysis. High level-flowcharts can also suggest other techniques that might not be available in one’s laboratory, but should be considered.
In order to improve the manufacturing process with copper wire, some manufacturers are experimenting with and implementing palladium-coated copper wire. One big reason we might consider palladium-coated copper wire is to reduce oxidation. Copper wire oxidizes in an oxygen environment (like an open assembly test area) so one solution is to coat the wire with an element like palladium. The palladium needs to be the thick enough to prevent oxidation, but thin enough to prevent changes in wire behavior, like changes in resistance, flexibility, intermetallic formation, and so on. The big advantage of palladium-coated copper wire is that the shelf life for wire bonding applications is weeks, rather than days for bare copper wire.
If we look at the phase diagram for palladium and copper, we can see why some of the problems exist. Palladium is a substitutional element in the copper lattice. If we have a 25µm diameter wire with a 0.1µm palladium coating, then this translates to a 2.2 percent atomic concentration of palladium in copper. This substitution will raise the Vicker’s Hardness Number of the copper by about 5. The solidus and liquidus lines are close to one another. Furthermore, turbulent mixing of the elements occurs during the heating phase. This leads to situations where the two elements can erratically segregate in the free air ball.
Figure 2 shows segregation of the palladium in the free air ball. Notice that we don’t form alloys; the copper and palladium exist as separate elements up to the liquid phase. Also notice that at low currents, or less heat, the palladium tends to clump into smaller regions. The grey areas indicate palladium-rich areas. At higher currents, the palladium does mix more randomly and deeper into the free air ball itself. In general, the mixing leads to higher hardness of the ball itself, making bonding more problematic.
The electronic flame off (EFO) procedure needs to be modified for palladium-coated copper. Palladium has a higher melting point than copper, so the palladium doesn’t form a solid solution with the copper. Therefore, the free air ball doesn’t contain uniformly distributed palladium. Engineers can adjust the profile of the EFO to create a free air ball with palladium on the surface. The properties of the free air ball depend on many factors including the flow rate of oxidation protection gas, the EFO current, the firing time and the gap between the tip of wire and the EFO wand. With a proper EFO, one can improve the corrosion resistance as compared to a bare copper ball. Some researchers have reported that one can form an EFO ball in pure nitrogen without requiring forming gas.
There are some consequences to switching to palladium-coated copper. Copper wire is not a ductile as gold wire, so package flexing becomes more of an issue. Package flexing can lead to loss of adhesion and wire fatigue near the stitch bond on the package lead frame.
Although there are some concerns, the palladium coating not only reduces oxidation but it can also improve corrosion resistance, which can improve packaging reliability in environments where moisture might be a concern.
 H. Clauberg, et. al., "Wire Bonding with Pd-Coated Copper Wire," IEEE CPMT Symposium Japan, pp. 1-4, 2010
 L. J. Tang, et. al., "Pitfalls and Solutions of Replacing Gold Wire with Palladium Coated Copper Wire in IC Wire Bonding," IEEE ECTC, pp. 1673-1678, 2011
Q: MM and HBM are common requirements for our products (power amplifiers/low noise amplifiers), but is CDM also a must during qualification?
A: CDM is an important test method when the products you produce will go through a lot of automated assembly and testing. I am not sure if that is the case for your products. You may have to check with your product engineers to determine which markets your parts go into. In general, power amplifiers would not be as sensitive to CDM damage as low noise amplifiers, but most amplifiers have ESD-sensitive inputs.
Please visit http://www.semitracks.com/courses/analysis/fundamentals-of-yield.php to learn more about this exciting course!
(Click on each item for details).
Semiconductor Reliability on January 23-25, 2013 (Wed.-Fri.) in San Jose, CA, USA
Failure and Yield Analysis on January 28-31, 2013 (Mon.-Thurs.) in San Jose, CA, USA
EOS, ESD and How to Differentiate on February 4-5, 2013 (Mon.-Tues.) in San Jose, CA, USA
Introduction to Polymers and FTIR on February 4-5, 2013 (Mon.-Tues.) in San Jose, CA, USA
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at firstname.lastname@example.org.
To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (email@example.com).
We are always looking for ways to enhance our courses and educational materials.
Home > Newsletters > 2012 December Newsletter