This article is a continuation of last month’s article on lead-frames. Today, we mainly use plated leadframes. Plated leadframes can help improve adhesion of the die attach, wire bonds, and mold compound, and improve the solderability of the leadframe. The plating materials need to meet environmental regulations associated with the Removal of Hazardous Substances (RoHS), and they need to be inexpensive. RoHS requirements eliminate the possibility of lead, so that means we must use other plating materials. Figure 1 (below) shows an example of a leadframe plating system. In order to reduce costs, some companies plate the leadframe prior to stamping. This is called a pre-plated leadframe.
Many companies use tin as a leadframe plating. The leadframe supplier deposits a plating layer between 7 and 20 microns thick. This improves solderability. However, copper-tin intermetallics can form and interfere with the reliability of the solder joint, and can aid in the growth of tin whiskers, another reliability problem. Some companies will anneal or fuse the tin plating to reduce this problem. Some companies will also use silver plating. The silver plating is on the order of 2.5 to 8 microns thick, and the assembly site deposits this after mold on the exposed portion of the leads. Some companies use a nickel-palladium-gold plating to prevent the intermetallic growth. The nickel-palladium-gold layer is quite thin, with the nickel between 0.5 and 2 microns thick, the palladium between 10 and 100 nanometers thick, and the gold only 3 to 9 nanometers thick, to reduce costs. This process is done by the leadframe supplier.
One technique to improve adhesion is to change the plating finish. One can roughen the nickel layer through a chemical etch before depositing the palladium. This improves adhesion, and is particularly effective with downbonds. This is also important with copper wire since it has lower fatigue strength. However, a rough leadframe costs 15-30% more.
Rough leadframes help control mold and die attach delamination. The rough leadframe keeps the stress low on the ball and stitch bonds to prevent lifted ball and broken stitch bonds. It also protects the thermal path. Figure 4 helps to illustrate this. The upper drawing shows a schematic cross section of the nickel-palladium-gold pre-plated leadframe, and the lower figures show scanning electron microscope (SEM) images of the standard and rough leadframes.
The scanning acoustic microscope images in Fig. 5 show how a rough leadframe can improve adhesion. The samples on the left show significant areas of red after undergoing the JEDEC Level 3 Moisture Sensitivity Stress Test. The red indicates delamination has occurred. The samples on the right show very little delamination. The red mark on each package in the lower right corner is an artifact of the mold release process, and is not associated with leadframe delamination.
In conclusion, we briefly discussed the different types of leadframes used in packaging semiconductor devices. We learned that the industry primarily uses copper and copper alloys because of their lower resistance. We also discussed several types of platings, including tin, silver, and nickel-palladium-gold coatings, and their advantages and disadvantages. Leadframe technology is an older technology that is mature, but it is still widely used in the industry. We still make billions of devices per year with leadframes, and will continue to do so for the foreseeable future.
Quiescent Power Supply Current (IDDQ) is a powerful way to examine a component during a failure analysis effort. Many types of defects can be identified from the IDDQ signature. We won’t go into why this is so here, as there is more information on this topic on our Online Training site. However, we will discuss the nature of the IDDQ measurement and what it tells us.
First, let’s discuss how to make a Quiescent Power Supply Current (IDDQ) measurement on a bench setup. To perform this test, one needs a curve tracer or a parameter analyzer, a switchbox capable of connecting to the curve tracer and the device, and the device to be tested. The analyst should then place the IC in a non-contention state. A non-contention state is one where there are no transistor outputs trying to drive a logical high and a low at the same time on the same node. In order to remove the contention, it may be necessary to clock the IC or input a few vectors to the appropriate inputs. The analyst should tie all of the inputs to either VDD or VSS, float all of the outputs, and sweep the voltage on the VDD side from the maximum rated supply voltage down to zero. This will yield a curve similar to the curve shown in the lower left portion of this slide.
Figure 2 shows some actual examples of IDD-VDD curves. These are all taken from microprocessor analysis work done several years ago. The microprocessors are 0.5µm CMOS circuits with approximately 800,000 transistors. The curve on the upper left has an obvious parabolic shape to it. Subsequent failure analysis localized the problem to a gate oxide short in an n-channel transistor within the random logic. The curve on the upper right shows a linear shape. In this case, the defect was localized to a high resistance short between VDD and VSS. In the example in the lower left, the IDD-VDD curve exhibits an exponential characteristic. The current is well within the specified limits at 3.3 volts and 5.0 volts, but it increases rapidly at about 5.5 volts, somewhat sooner than a defect-free circuit. This leakage is due to a soft pn junction, and possibly attributable to electrostatic discharge damage. The IDD-VDD curve on the lower right has an erratic shape to it. We created the IDD-VDD curve by sweeping from the supply voltage down to zero. Notice that the current starts at a low value, then jumps high. It then meanders erratically downward until about 1 volt, where it then drops to a low value. An erratic, time-varying current is indicative of an open circuit defect.
Q: How accurate is an IDDQ vs. VDD curve trace in determining the actual defect on an IC?
A: We actually discuss this test and defects in this month's Technical Tidbit. IDDQ vs. VDD can help the analyst separate opens from shorts, and identify various types of shorts, but the accuracy level is only around 85% or so. Although IDDQ is a great test for establishing the direction of an analysis, it is even less accurate by itself in determining what the actual defect will be. One will need further analysis to identify the actual defect.
Please visit http://www.semitracks.com/courses/processing/cmos-bicmos-and-bipolar-process-integration.php to learn more about this exciting course!
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ESD Design and Technology on February 11-13, 2014 (Tues.-Thurs.) in San Jose, CA, USA
Semiconductor Reliability on February 11-13, 2014 (Tues.-Thurs.) in San Jose, CA, USA
Failure and Yield Analysis on February 17-20, 2014 (Mon.-Thurs.) in San Jose, CA, USA
Wafer Fab Processing on February 18, 2014 (Tues.) in San Jose, CA, USA
CMOS, BiCMOS and Bipolar Process Integration on March 25-26, 2014 (Tues.-Wed.) in Austin, TX, USA
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