Another contender as a future non-volatile memory technology is Resistive Random Access Memory, sometimes shortened to RRAM or ReRAM. A prototype RRAM chip is shown in Figure 1. Several major manufacturers are working on RRAM, including: Samsung, Micron, Macronix, and Elpida Memories. The technology is somewhat similar to Conductive Bridging RAM and Phase Change Memory, which we discussed in the previous issue. IMEC in Belgium has also done extensive research into this technology.
The basic concept is that one can create a conducting path through a dielectric layer by applying a high voltage (see Figure 2). The conducting path or filament can be reset, restoring the high resistance path and reformed to create a low resistance path at will. This filament path may actually be multiple paths, according to researchers. There are different types of materials that can exhibit this behavior. They include perovskites, chalcogenides, and transition metal oxides. Some of the leading transition metal oxides include nickel oxide, titanium oxide, tungsten oxide, hafnium oxide, and heterostructures such as aluminum oxide/titanium oxide. Ironically, even silicon dioxide can be used for this application. The failure mechanism engineers try to avoid in standard CMOS, time-dependent dielectric breakdown, is the mechanism by which the programming occurs.
RRAM has the potential to become the front runner for future memory technologies. RRAM can operate much faster than Phase Change Memory. The switching time can be on the order of 10ns. Compared to MRAM, RRAM has a much smaller cell size. The cell size is less than 8F2, where F is the smallest feature size. It can also function at lower operating voltages than standard flash memories. RRAM also has the potential to scale down below 30nm. While standard flash memory is now below 30nm, the cell size is larger, so RRAM can still accommodate more cells in the same silicon area. Researchers believe that the mechanism might involve oxygen motion, which might allow for scaling down to as low as 2nm. The filament dimensions during the forming process are also key factors to a stable, reliable device(1)
(1) G. Bersuker, et. al., "Diode-less Nano-scale ZrOx/HfOx RRAM Device with Excellent Switching Uniformity and Reliability for High-density Cross-point Memory Applications," Proc. Int. Elec. Dev. Meeting, 2010 pp. 452-455.
Usually, wafers are ground down before the sawing operation. However, some organizations have been exploring a process where the sawing operations occur first, followed by the backgrinding operation. This is sometimes referred to as "Dice Before Grinding", or DBG. The conventional grind before sawing is shown in the upper row. Three variations of the DBG approach are shown in the lower rows. DBG can be done with or without Chemical Mechanical Polish, or CMP. CMP can be useful when a higher quality interface is needed between dice. DGB can also be accomplished using standard wafer saw processes, or with reactive ion etching.
One concern with thin dice is how to handle them. The dice are especially prone to damage during pick and place operations. The key is to initiate the peeling process from the backing tape without damaging the dice. This diagram shows an approach to doing just that. This process involves raising and then lowering the ejector assembly. By raising it, one can initiate the peeling process at the edge of the die. By then lowering the ejector assembly, one can achieve a controlled peeling process in which the backing tape peels away from the die, but the die is held in position by the ejector pins.
Q: I am detecting sulfur on the top of packaged devices as well as on the bond pads of printed circuit boards in our manufacturing process. What might be causing this contamination?
A: There are several common sources of sulfur in PCB manufacturing and assembly. They include: outgassing of elastomers vulcanized with sulfur, contamination in the PCB board itself, sulfur in the solder resist material, stop- off lacquer, contamination from paper or paperboard (cardboard) materials, and industrial environments or city environments with high sulfur or sulfide concentrations.
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(Click on each item for details).
Failure and Yield Analysis on February 28 - March 3, 2011 in San Jose, CA, USA
Wafer Fab Processing on February 28 - March 3, 2011 in San Jose, CA, USA
IC Packaging Design and Modeling on March 7-9, 2011 in San Jose, CA, USA
Failure and Yield Analysis on March 10-11, 2011 in Kuala Lumpur, Malaysia
Wafer Fab Processing on March 14-18, 2011 in Kuala Lumpur, Malaysia
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