Feature Article - Failure Analysis Procedures, Part 4 - By Christopher Henderson

This article is the conclusion of our series on failure analysis procedures. As we have been discussing over the past several months, sometimes failure analysts can best understand the FA procedure for a component by thinking about the process in terms of the type of failure. This is a flowchart that describes how to analyze a short or a leakage failure at either the wafer or package level. Both flows are very similar, so we will discuss them together.

Figure 1 shows a flowchart that describes how to analyze a short circuit. We begin by examining the device with a curve tracer to check for the short. The pin or bump exhibiting the short should be identifiable from the automatic test equipment (ATE) datalog for the device. If the device has not been tested it should be tested using ATE to confirm the failure. We can also do this directly with the curve tracer, but it can be very time-consuming for a device with many pins, bumps, or bond pads if we’re doing this at the wafer level. The flow now branches if we have a packaged device. If we have a packaged device, we can perform x-ray radiography and scanning acoustic microscopy to look for a wire or bump short, void, crack or some other anomaly. There are other advanced techniques one can try like time domain reflectometry or Superconducting Quantum Interference Device (SQUID) microscopy as well to help localize this type of problem. If we are able to locate a shorted wire, shorted ball, or other obvious anomaly, we can document it and proceed to the report generation. If there is no obvious defect or problem, then the problem most likely lies on the die itself. It makes sense to decapsulate the device to expose the die surface. After decapsulation, one should re-check the pin in question to make sure the short is still present. If the failure is no longer present, then an optical or SEM inspection might be in order at this point to look for anything that might have been missed. If the failure is still present, then we can begin to isolate it on the die. If the package structure is still present, we can use a technique like Liquid Crystal Thermography for a front-side analysis approach, Light Emission, or laser-based techniques like TIVA (Thermally-Induced Voltage Alteration) or OBIRCH (Optical Beam-Induced Resistance Change) to localize the short from both the front or the backside. However, if the package structure is no longer present, then we will need to use a more traditional technique like passive voltage contrast. We then enter a loop where we remove overlying layers to expose the layer of interest, and perform voltage contrast. We can continue in the loop until we identify the failure site or reach the silicon substrate. If we don’t see incorrect contrast, then we can remove the chip layers down to the next metal layer in the node, or down to the upper-most metal layer in the next candidate. We would continue this process down through the backend of the process, or through the interconnect and dielectric layers. Once we see incorrect contrast or the defect itself, we can determine if we need further analysis. This might involve a cross-section or liftout of material. We can then examine the defect with the SEM or TEM as appropriate. If we do not see the defect after removing all of the interconnect and dielectric layers, we can decorate the substrate to highlight potential defects in the silicon. At this point, we can write up our findings in a failure analysis report.

Figure 2 shows a flowchart that describes how to analyze a leakage failure. This flowchart is quite similar to the flowchart we showed in Fig. 1 to describe how to analyze a short circuit failure. Therefore, we will just point out the differences. The main difference in looking for a leakage path as opposed to a short is the magnitude of current involved. A leakage path is likely to have a much lower current than a short. Furthermore, a leakage path may still allow the device to function properly. Therefore, electrical test techniques like IDDQ (Quiescent Power Supply Current) testing become more important. Furthermore, the curve tracer also becomes more important as characterization tool. A leakage path in the package can be quite difficult to detect. Superconducting Quantum Interference Device (SQUID) microscopy is an important technique to help localize this type of problem. Leakage isolation at the die level can also be challenging. Maintaining the package structure becomes more important, since techniques like Passive Voltage Contrast are less effective. If the package structure is still present, we can use techniques like Liquid Crystal Thermography for a front-side analysis approach, Light Emission, or laser-based techniques like TIVA (Thermally-Induced Voltage Alteration) or OBIRCH (Optical Beam-Induced Resistance Change) to localize the leakage path from both the front or the backside. Analysts use passive voltage contrast to identify opens and shorts. If we don’t see incorrect contrast, then we can remove the chip layers down to the next metal layer in the node, or down to the upper-most metal layer in the next candidate. This may require some manual probing with probes in the SEM or an Atomic Force Probe system. We would continue this process down through the backend of the process, or through the interconnect and dielectric layers. Once we see incorrect contrast, identify the defective transistor, or interconnect segment, or the defect itself, we can determine if we need further analysis. This might involve a cross-section or liftout of material. We can then examine the defect with the SEM or TEM as appropriate. If we do not see the defect after removing all of the interconnect and dielectric layers, we can decorate the substrate to highlight potential defects in the silicon. At this point, we can write up our findings in a failure analysis report.

While FA becomes more challenging as we go to smaller and smaller feature sizes, there are some standard flows that work well. These five FA flows we have discussed in this and previous articles can help the analyst structure their work in a logic manner to increase the chances for success. If you would like to learn more about FA processes, we would encourage you to sign up for access to our Online Training System. The system contains a number of presentations that talk not only about this topic, but also other procedures used in failure analysis. The link to learn more is shown here: http://www.semitracks.com/online-training/