This article provides an introduction to quality for semiconductor components. Quality is an important aspect of semiconductor manufacturing. Customers expect high-quality components, and one must design quality processes, test for quality, and create procedures to handle issues of a quality nature that might arise.
Most companies define and implement quality at the highest levels within the organization, since customer perceptions are important. Anywhere the customer directly interacts with the company or indirectly feels the impact of the organization on quality, we define management practices to measure, control and improve the end experience for the customer. This diagram shows the impact of quality on the major organizations within the company. This diagram shows the roles of management, product engineering, other support functions, and manufacturing (see Figure 1).
Most manufacturers will develop a set of documentation around quality. This is an example of some of the topics that one might address when developing quality documentation.
These are the important components of a quality system:
An important aspect to quality is the time-zero quality. Many engineers also refer to this as initial quality. For a component, it should be free of defects, both visual and electrical. It should perform all of its functions correctly. A component that works partially would be low quality. For instance, if 5 percent of a shipped 12-bit analog-to-digital converter converted the 6 most significant bits correctly, but not the 6 least significant bits, we would think of this component as a low quality component. Not only should the component perform all of its functions, but it should be able to do it over its operating conditions. For instance, if a component is specified to work from 0 to 70°C, but only works correctly up to 65°C, then this would be a low-quality component. A good way to think about this is to think about your expectations with a new car. You expect not only the engine to start are run correctly, but also the brakes to work correctly, the power mirrors, heater, door locks and so on. You also expect it to start on cold mornings, as well as run properly on a hot day.
The second aspect of quality is the time component. A high quality semiconductor component should work correctly for its intended lifetime, whether that be 4 months or 4 decades. It should pass its functional and parametric testing at the end of its life, just as it did at the beginning of its life. The failure rates should be at or lower than expected. For instance, we would consider a component to be low quality if the observed failure rate was 60 FIT (failures in time) when it should have been 50 FIT. There should also be no degradation or drift in parameters. This can lead to system failures. Again the automobile analogy can work well here. After 5 years and 75,000 miles, we would think about the automobile on the left as being a higher quality automobile, compared to the one on the right.
There are many steps to a qualified product. We can consider two areas that affect the qualified product: the product qualification process and the quality system. Under product qualification, we can define a technology reliability component, which tracks the goodness of the wafer fab process to create a working product, a product reliability component, which includes specific items related to the product design and its package, functionality, or the ability of the component to work over a specified operating range, and manufacturability, or the ability to create a high-yielding component that can be consistently produced. Under the quality system, we have the process for creating a qualified product, monitoring of the line for potential problems, change management to control product revisions, and returns management, to correct problems that might occur. These systems should lead to a quality product, if implemented and monitored correctly.
Technology qualification is the qualification of the chip fabrication process, so this activity deals with the die. Engineers are primarily concerned with the failure mechanisms, so they research existing and potential new failure mechanisms, develop models for them, and then perform accelerated stress tests to understand the distribution of the failures due to those mechanisms. Then with the distribution data and the model, they can predict when a population of chips might fail due to this mechanism. They can then combine the various failure mechanisms and the information they have on the use profile for the end products, and generate an estimate of the reliability. This approach is sometimes referred to as knowledge-based qualification.
Let’s briefly turn our attention back to standards based qualification. This is a common approach, and is still used widely in the industry. There are four major standards-based qualification processes used in the industry. The United States Military uses MIL-STD (pronounced “mil-standard”) 883 for qualification. JEDEC, the Joint Electron Device Engineering Council, developed JESD47, a stress-based qualification standard. The Automotive Electronics Council has a standard for qualification, and Zentralverband Elektrotechnik- und Elektronikindustrie (ZVEI), or the Central Association of Electrical and Electronics Industry in Germany, also has a qualification standard that is used for some European electronics systems, including automotive systems. Several of these standards are discussed elsewhere in this workspace.
Qualification provides upfront evidence that the product will work as intended in the application, but how do we ensure quality during production? Things can change, so we need a process to evaluate quality while the product is manufactured. We do this through testing. The more thorough the testing we do, the more evidence we can provide that we are shipping a quality product. Of course, the product has to pass the electrical testing.
There is a simple equation one can use to model the defect level, or quality as a function of yield and test coverage. Basically, the defect level will drop to zero if the yield can reach 100%, or if the test coverage can reach 100%. This model is known as the Williams and Brown model and is a simple way to make these estimations. One can do it for separate test sections like stuck-at-faults, transition faults, and IDDQ faults, or as an integrated fault coverage.
For reliability prediction, engineers will use the results from the die-level accelerated testing and package modeling to develop an estimate of what the reliability should be at the outset. Once the manufacturer starts producing components, the reliability engineers can use the results from the standards-based testing to provide a more refined estimate of the reliability of the component. There are numerous factors to consider when doing this. First would be the scale factors to map from the test die to the product die. Parameters such as chip area, gate area, transistor count, metal lengths, and package size and thickness all will play an important role. Also, power dissipation and heat dissipation play an important role. The customer use conditions and mission profile are critical as well. Parameters such as a thermal profile, the on-time of the component and system, the number of cycles, the mechanical stress, as well as the possibility for overstress like Electrical Overstress (EOS), Electrostatic Discharge (ESD) and latchup will all impact the reliability of the component.
This brings us to the qualification process itself. A part is considered qualified when all of the qualification objectives are met. These can be standards based, or knowledge-based objectives. If they’re not met, then one needs to define a reliability and/or manufacturing screening strategy to remove potential failures from the population. Second, one might define a product guardband strategy to ensure that a mechanism does not proceed far enough to cause product failures. This strategy will need to be validated through testing to demonstrate that it is effective. If the strategy is deemed effective, and your customer agrees on the strategy, then one can qualify the product with these additional screens and guardbands.
All customer returns should be treated seriously. Most companies have an established method for initiating and processing returns through a Return Material Approval or RMA process. Once the manufacturer receives the returned product, it undergoes appropriate testing and analysis to confirm the failure or problem. Those steps usually include:
Many manufacturers use an information system to track customer returns. In a large company, one might compile and distribute monthly customer incident metrics. These can then drive continuous improvement. Some companies also use failure mechanism paretos to drive continuous improvement in the various quality areas.
Failure Analysis is a critical step in the process where the analyst works to uncover physical evidence that clearly identifies the cause of failure. The analyst seeks this evidence through investigation on a case-by-case basis of failed integrated circuits. He or she uses electrical and physical analysis to perform an array of straightforward but sophisticated analytical measurements and techniques. Using the appropriate equipment and work processes, the analyst can isolate the location of the cause of failure on the die and physically characterize it. Failure analysts need to collaborate with other engineering disciplines, e.g., product, test, design, assembly and process, in order to solve the analysis. The customer quality engineer and failure analysts communicate their progress, results and conclusions to both internal and external contacts so that the manufacturer can implement changes that will eliminate or at least mitigate the cause of failure.
In conclusion, IC quality is part of a larger corporate strategy. From an engineering perspective, the activities that primarily fold into a quality process include the manufacturing process, reliability engineering, the qualification process, test engineering, a robust return material tracking system, and failure analysis. Ultimately though, what the customer perceives as a whole from the manufacturer impacts their view of quality, so there are many intangible aspects to it. This includes support, service, and other functions beyond the engineering aspects we discussed in this section.
We wanted to make you aware of some developments with our Online Training System. We recently completed an upgrade of our system. We are also in the process of adding additional content into the system. In the new system you can log in more easily, access a wider range of videos, and easily run the presentations in an inline mode (which avoids the need for configuring a pop-up blocker), or run the presentations in full-screen mode (for easier viewing on small screens). The new system is also compatible with the iPad tablet, so look for content that can run on your iPad in the near future. The New Year is underway. Why not invest in yourself and purchase one-year access to the system? You can find out more information about our system and register at: http://www.semitracks.com/online-training/
Q: We are looking to develop the EBIC technique on our FA lab (we have a Kleindiek system) mainly on Silicon power device; any help or comments on our activities would be greatly appreciated (defect detected, technical details, limits, advantages over other methods…)
A: This is an overlooked technique that is great for isolating failures. It can be especially useful in conjunction with a nanoprobing solution in the SEM, like you mention. Another approach is to use an AFM Probing System (Multiprobe is a manufacturer of this type of system). If you do a lot of fault localization, then this can be a great way to isolate things further. We discuss this technique in our Online Training System, and can do a one-day course on this topic as well.
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CMOS, BiCMOS and Bipolar Process Integration on March 25-26, 2014 (Tues.-Wed.) in Austin, TX, USA
Semiconductor Package Design, Simulation and Technology on April 7-9, 2014 (Mon.-Wed.) in San Jose, CA, USA
Product Qualification on April 15-16, 2014 (Tues.-Wed.) in San Jose, CA, USA
Failure and Yield Analysis on May 5-8, 2014 (Mon.-Thurs.) in Munich, Germany
MEMS Technology on May 12-13, 2014 (Mon.-Tues.) in Munich, Germany
Semiconductor Reliability on May 12-14, 2014 (Mon.-Wed.) in Munich, Germany
Product Qualification on May 15-16, 2014 (Thurs.-Fri.) in Munich, Germany
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