Last month, we delved a little deeper into Thermal Processing, covering [Equipment and Processing]. This month we’ll focus on some issues and effects associated with thermal processing. While thermal oxidation is primarily driven by temperature, there are second order effects that modify oxide growth. We will review these.
As a quick review, we show the basic Deal-Grove model here: where x is the oxide thickness, B is the parabolic rate constant, B over A is the linear rate constant, and tau is a factor to account for oxide present at the start of the oxidation. Let’s take a closer look at the inputs to constants A and B.
In order to solve for B and A, one must first know the values of C1, C2, E1, and E2. These values can be determined experimentally. This table shows values for the four constants under three different oxidation conditions: dry oxygen, wet oxygen, and steam. Wet oxygen is a condition where oxygen is bubbled through water prior to entering the oxidation furnace. These constants are for one atmosphere total pressure. The constant C2 is different depending on the crystal face exposed. In general, the <111> crystal face exposed results in a C2 constant that is about 1.68 times greater than with the <100> face exposed.
This slide shows the rate constants B and B over A as a function of temperature. In general the rate constants trend higher with increasing temperature. Also, the B over A rate constant has a higher slope than the B constant.
There are three basic factors which affect the oxidation process at the surface: temperature, availability of the oxidizing species, and the surface potential of the wafer. As is the case with many reactions, the rate of oxidation is greater at higher temperatures. The availability of oxygen at the surface is also important. Finally, the surface potential or surface energy can come into play. The crystal orientation, the silicon doping concentration, and any pre-oxidation surface treatments can affect the electro-chemical potential of the surface, increasing or decreasing the rate of reaction.
This graph shows the oxide growth in dry oxygen. The graph shows the oxide thickness as a function of oxidation time for several different growth temperatures. Notice that the oxide growth is approximately a straight line on a log-log plot. Also notice that the growth rates on <111> silicon are slightly faster than on <100> silicon. This is because the electro-chemical potential is slightly greater for the <111> face.
This graph shows the oxide growth in pyrogenic (pronounced pie-ro-jen-ik) steam. The graph shows the oxide thickness as a function of oxidation time for several different growth temperatures. Notice that the oxide growth is approximately a straight line on a log-log plot. The growth rates are about a factor of ten faster than shown on the previous slide in dry oxygen. Also notice that the growth rates on <111> silicon are slightly faster than on <100> silicon. This is because the electro-chemical potential is slightly greater for the <111> face. We also show a growth line for undoped polysilicon at 750°C.
The stresses generated by the TSV not only affect the interconnect ends, but they also affect the stress in the silicon. In fact, sufficient stress is generated to result in transistor mobility variations. In today’s nanometer-scale technologies, a slight variation in mobility in some transistor can result in the design not working. Researchers at CEA-LETI in France have modeled the effects of stress. Here are two examples of modeling work showing how the TSVs affect stress during temperature cycling, and the molding process.
In these examples, the silicon die with TSVs is stacked on top of a MEMS chip. Notice the high stress values at the corner, but even these are significantly less than the stress values associated with the maximum point in the vicinity of the TSVs. This requires coordination between the silicon chip designers and the packaging engineers – an activity we normally refer to as chip-package co-design. The result might mean the creation of Keep Out Zones (KOZs) for sensitive transistors.
Q: I have heard the term NSOL and NSOP. What do they mean?
A: NSOL and NSOP mean Non Stick On Lead and Non Stick On Pad respectively. Lead refers to the exposed leadframe, and Pad refers to the bond pads on the integrated circuit. This can happen for several reasons, but typically occurs when the die attach bake process releases volatile compounds, which coat the leadframe and bond pads. This can interfere with the bonding process, leading to a wire bond that doesn't bond correctly to the bond pad or lead frame.
Please visit http://www.semitracks.com/courses/reliability/semiconductor-reliability.php to learn more about this exciting course!
(Click on each item for details).
Failure and Yield Analysis on April 27-30, 2015 (Mon.-Thurs.) in Munich, Germany
Semiconductor Reliability on May 4-6, 2015 (Mon.-Wed.) in Munich, Germany
EOS, ESD and How to Differentiate on May 7-8, 2015 (Thurs.-Fri.) in Munich, Germany
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at email@example.com.
To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (firstname.lastname@example.org).
We are always looking for ways to enhance our courses and educational materials.