Feature Article - Failure Analysis Procedures, Part 3 - By Christopher Henderson

This article is a continuation of last month’s article. As we discussed last month, sometimes failure analysts can best understand the FA procedure for a component by thinking about the process in terms of the type of failure. This is a flowchart that describes how to analyze an open circuit failure at either the wafer or package level.

Figure 1 shows a flowchart that describes how to analyze an open circuit. We begin by examining the device with a curve tracer to check for the open. The pin or bump exhibiting the open should be identifiable from the automatic test equipment (ATE) datalog for the device. If the device has not been tested it should be tested using ATE to confirm the failure. We can also do this directly with the curve tracer, but it can be very time-consuming for a device with many pins, bumps, or bond pads if we’re doing this at the wafer level. The flow now branches if we have a packaged device. If we have a packaged device, we can perform x-ray radiography and scanning acoustic microscopy to look for a void or crack. There are other advanced techniques one can try like time domain reflectometry or Superconducting Quantum Interference Device (SQUID) microscopy as well to help localize this type of problem. If we are able to locate a broken wire, lifted ball, or other obvious anomaly, we can document it and proceed to the report generation. If there is no obvious defect or problem, then the problem most likely lies on the die itself. It makes sense to decapsulate the de- vice to expose the die surface. After decapsulation, one should re-check the pin in question to make sure the open is still present. If the failure is no longer present, then an optical or SEM inspection might be in order at this point to look for anything that might have been missed. If the failure is still present, then we can begin to isolate it on the die. If the package structure is still present, we could use a laser-based technique like Seebeck Effect Imaging to localize the open. However, if the package structure is no longer present, then we will need to use a more traditional technique like passive voltage contrast. We then enter a loop where we remove overlying layers to expose the layer of interest, and perform voltage contrast. We can continue in the loop until we identify the failure site or reach the silicon substrate. Analysts use passive voltage contrast to identify opens and shorts. If we don’t see incorrect contrast, then we can remove the chip layers down to the next metal layer in the node, or down to the upper-most metal layer in the next candidate. We would continue this process down through the backend of the process, or through the interconnect and dielectric layers. Once we see incorrect contrast or the defect itself, we can determine if we need further analysis. This might involve a cross-section or liftout of material. We can then examine the defect with the SEM or TEM as appropriate. If we do not see the defect after removing all of the interconnect and dielectric layers, we can decorate the substrate to highlight potential defects in the silicon. At this point, we can write up our findings in a failure analysis report.