This month we will cover an overview of decapsulation. For standard plastic packages, there are two basic methods for exposing the die surface—a standard chemical etch by hand, or an auto- mated approach that uses a machine called a Jet Etch. The manual approach is quite inexpensive. Assuming one has the appropriate chemical handling facilities such as an acid storage cabinet, appropriate protective gear, beakers, and a fume hood, the etch can be accomplished with a small amount of red fuming nitric acid. Red fuming nitric acid is quite dangerous, and should not be handled carelessly. One should always wear the appropriate protective clothing when performing a chemical etch of this type. The analyst should wear acid-resistant gloves, a smock, goggles or more preferably, a face shield, and closed-toed shoes. The red fuming nitric acid must also be heated to approximately 80°C to achieve decent results. Red fuming nitric acid emits toxic vapors, so this type of etch should always be performed in a fume hood with a working exhaust system. An etch performed by hand can lead to uneven results. It is preferable to practice on one or more parts before attempting the etch on the actual failed device. In contrast the Jet Etch machine can use either sulfuric or nitric acid. The machine heats the acid internally and uses a small amount to accomplish the etch. Although it is best to place the machine in a fume hood, it can be operated safely outside of one. The biggest drawback is the initial expense of the system. A new Jet Etch system will cost between $35,000 and $50,000 (US). However, once purchased, the machine will use less acid and deliver more consistent results than can be done by hand.
Jet Etch decapsulation is normally the preferred method for decapping plastic packaged parts. The system can accommodate a variety of package configurations and die sizes. It is also safe to use, fast, and easy to operate.
The plumbing for a Jet Etch system is shown in Figure 2. Acid is pumped from one or both of the acid supply containers into the pump mix/flow control chamber, where the acid is heated and mixed. The hot mixture then travels to the chamber where it is then sprayed onto the surface of the plastic package. A gasket can be used to help control the area over which the acid contacts the package. The heat exchanger helps to cool the package during the etch process. The used acid and the waste then travel to an acid waste bottle. A waste diversion valve can help make the job of disposal easier by separating various types of waste products from decap to decap operation.
Here is an example of the results of a Jet Etch machine. Figure 3 is an SEM image of a portion of the die surface, bond wires, and mold compound after a Jet Etch. If performed properly, a Jet Etch should leave the device electrically intact, with little or no corrosion. There should also be no damage to the die. Most problems occur when a second etch is performed without thoroughly drying the part after the first etch. The moisture from the rinse after the first etch can react with the acid and exposed aluminum or copper, damaging the bond wires and bond pads. The Jet Etch can also quickly decapsulate a device. The process takes sixty seconds or less, and therefore, causes limited exposure to heat and alteration of failure mechanisms sensitive to heat, such as charge buildup in the oxides.
The Jet Etch system can be used on a wide variety of different package types. Figure 4 shows some of the different package types that can be opened with a Jet Etch system. Analysts control the size of the opening by gaskets they place on top of the package to limit the extent of the acid interaction.
Many of today’s power semiconductor components, microprocessors, and ASICs reside on large dice. These dice occupy a disproportionately large part of the overall package volume. As such, the Jet Etch process can easily overetch the package sidewall, causing acid to leak out into the Jet Etch machinery and further damage to the package. Large die often require additional support or initial milling to preserve the package and its electrical integrity.
If you want to learn more about these techniques, including how to deal with newer materials like copper wire, consider enrolling in our Online Training System. We cover this topic in more detail, as well as dozens of other topics in failure analysis and reliability. You can learn more about this system on our web site (http://www.semitracks.com/online-training/).
An increasing problem with modern ICs is their susceptibility to soft errors. A soft error can be caused by an alpha particle striking a sensitive region on a circuit, like a memory cell or register, creating a temporary logical error in the circuit. Alpha particles can come from a variety of sources, but those sources need to be in close proximity to the active transistors in order for the alpha particles to create the charge necessary to cause an error. A leading cause of alpha particles that cause this problem is contamination in the solder bumps and plating materials used to connect the die to the package leadframe or substrate. In order to minimize this problem, some manufacturers have turned to "Low alpha" or "Low emission" materials. Basically, a Low alpha material is a material that has undergone more extensive purification to reduce the contamination level of radioactive elements. These images show examples of some of the materials for which engineers create low emission variants.
While not all applications require this care with materials, systems that must operate without errors, or systems with large amounts of memory, can require these materials to avoid potential problems.
Q: Will SOI be the path forward for continued CMOS scaling?
A: This is a highly complex question and the source of a lot of debate within the industry. Currently, the thinking is that FinFET technology provides a better path forward because the fin structure permits better channel electrostatic control. However, Fully Depleted SOI (FDSOI) is a less complex process, and would provide a platform for other advances, like Monolithic 3D integration and Silicon Photonics. SOI uses a more expensive substrate, so cost-sensitive applications may not be able to go this route. Stay tuned over the next several years to see how this will play out.
Please visit http://www.semitracks.com/courses/processing/cmos-bicmos-and-bipolar-process-integration.php to learn more about this exciting course!
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ESD Design and Technology on February 11-13, 2014 (Tues.-Thurs.) in San Jose, CA, USA
Semiconductor Reliability on February 11-13, 2014 (Tues.-Thurs.) in San Jose, CA, USA
Failure and Yield Analysis on February 17-20, 2014 (Tues.-Thurs.) in San Jose, CA, USA
Wafer Fab Processing on February 18, 2014 (Tues.) in San Jose, CA, USA
CMOS, BiCMOS and Bipolar Process Integration on March 25-26, 2014 (Tues.-Wed.) in Austin, TX, USA
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