In this section we’ll discuss a variant of chemical vapor deposition known as Low Pressure Chemical Vapor Deposition, or LPCVD. This technique is commonly used for materials like polysilicon and silicon nitride deposition.
There are two basic types of chemical vapor deposition: low pressure CVD and atmospheric pressure CVD. In a low pressure CVD reaction such as plasma-enhanced CVD, the surface reaction is reaction rate limited. In order to grow the appropriate thickness, the temperature and time must be closely controlled. We discuss PECVD in a section close by. In an atmospheric pressure CVD reaction, the reaction rate is mass transfer limited. In this situation the flow of the gas must be uniform. This means that wafers cannot be placed too close to each other; otherwise they will interrupt the flow of the reaction gas.
Low pressure CVD has two distinct advantages over traditional chemical vapor deposition. LPCVD can occur at lower temperatures than traditional CVD. This allows one to use CVD to deposit layers after lower melting temperature materials have already been deposited, like aluminum. Furthermore, one can lower the temperature further by adding energy to a CVD process. Plasma enhancement is a common method to do this.
Low Pressure CVD has several disadvantages. Cleanliness is a major problem. Particles can be generated as a result of gas phase reactions instead of surface reactions. Other disadvantages include rough surfaces, surface cleaning issues, the need for accurate temperature control, gas entrapment, and toxic, hazardous gases. There is also a general lack of understand of CVD processes. Standard oxidation reactions have been studied for decades, while CVD processes have only been studied for the past dozen years. Many processes are even newer. Finally, there is a lack of proper gas phase species for most metals.
Let’s move on and discuss the uses for LPCVD. The first one is silicon nitride. A quality silicon nitride layer is amorphous, dense, chemically and thermally stable, has a relatively high dielectric constant, and a low coefficient of thermal expansion. This film normally exhibits a high tensile stress, but it can be highly compressive in certain situations. The front-end-of-the-line process applications include creating a mask for selective oxidation of silicon like a LOCOS field oxide, creating a hard mask for the shallow trench isolation trench etch, creating an STI trench liner, and depositing ONO capacitor dielectrics in DRAMs. The back-end-of-the-line applications typically use PECVD, since one can use lower temperatures. We discuss that topic in a section close by. Basically, the deposition process involves reacting dichlorosilane and ammonia to produce a solid silicon nitride layer, and hydrochloric acid and hydrogen as exhaust gases. This occurs at temperatures between 700 and 800°C. In a hot-wall LPCVD reactor, one must compensate for depletion effects. The process is affected by many variables, each of which must be controlled for a favorable outcome.
Polysilicon is another important application for LPCVD. The applications include heavily doped polysilicon for MOS transistor gates, capacitor electrodes, local interconnect in MOS circuits, and bipolar transistor emitters. They also include lightly doped polysilicon for high value resistors used for cross-coupled feedback in SRAMs, and STI trench refill. Process engineers can deposit these films conformally over steep topography. The polysilicon film is composed of small grains of single crystal silicon separated by grain boundaries. The properties of each grain are quite similar to those of single crystal silicon. However, the behavior along the grain boundaries is quite different, with enhanced diffusion properties, dopant segregation, and trapping of charge carriers.
Polysilicon exhibits a much higher resistivity than single crystal silicon for the same doping level. This occurs because the dopants segregate along grain boundaries, leaving fewer dopant atoms within the grains. Also, defects in grain boundaries decrease carrier mobility and the grain boundaries are full of dangling bonds—some of which can trap free carriers. The deposition process involves pyrolysis, or thermal decomposition, of silane. This yields solid silicon on the surface, and hydrogen as an exhaust gas. Process engineers typically use a batch process in a hot-wall LPCVD furnace with these approximate values. Process engineers might dilute the silane with a hydrogen carrier gas, which suppresses the gas phase decomposition of silane because it is one of the reaction products. Also, gas phase decomposition is undesirable because the resultant silicon particles will rain down on the growing film, causing roughening. Therefore, the engineers use a modified set of deposition conditions used to deposit amorphous silicon, which yields a slower reaction.
In most applications, process engineers dope the polysilicon to lower its resistance. There are three methods to do this: furnace doping, ion implantation, and in-situ doping. In furnace doping engineers pre-deposit from a liquid, solid or gas, as this is an easy method for very heavy doping. The major downside to this approach is lack of process control. Ion implantation is the preferred method since one can select the energy to put the range at the center of the film and do the anneal with rapid thermal processing. In-situ doping is another option where one dopes during the deposition by adding doping gases like diborane or phosphine to the reactant gases. In a batch reactor this severely complicates the process control, but it is less of an issue in a single wafer reactor. One cannot do dual-doped polysilicon with this approach though, where one doped the polysilicon over the n-channel transistor differently than over the p-channel transistor.
Let’s move on and discuss LPCVD equipment. The hot-wall horizontal tube reactor is a common system for this process. It is used primarily for silicon nitride and polysilicon, the two materials we just discussed. It is very similar to an atmospheric oxidation furnace tube. These systems contain a long tube made from high purity silica, and a radiant heating system made from high resistance ceramic coils surrounding the tube. The gases are metered into the tube at one end, and exhausted at the other end. Process engineers mount the wafers in a fused silica boat, about 5 to 6 millimeters apart from one another. One typically loads between 100 and 200 wafers into the system at a time, which is possible because the environment is a surface reaction rate-limited process that doesn’t required equal mass transport to all areas of all the wafers.
A typical LPCVD system uses vacuum pumps and a pressure control system to maintain a constant pressure. They operate between 600 and 850°C, and pressures between one-quarter and two torr. The advantages to LPCVD include a relatively simple design, excellent economy, high throughput and good uniformity. The disadvantages of these systems include susceptibility to particle contamination, which necessitates frequent cleans, and the need to compensate for gas depletion effects.
This figure shows a basic schematic for an LPCVD tool, along with the vacuum system. Again, these systems can hold many wafers in the quartz tube, allowing for high throughput in the process. Since the tube is rather long, most systems will contain zones that can be individually controlled to ensure better uniformity.
The next figure shows an example of a CVD quartz tube that processes wafers in batch form in more detail. A low pressure CVD reactor consists of a quartz tube connected to a pump. The gas inlet is used to introduce the reactant gases as well as gases used to purge the system, such as nitrogen. The wafers are loaded through the door on the left. In a low pressure system, the wafers can be placed closer, as is shown here. A furnace encompasses the quartz tube. This heats the chamber, driving the reaction rate faster.
Today, process engineers also use cluster tools for low pressure CVD steps. Many manufacturers replaced their hot wall batch reactors for cluster tools in 300 millimeter and some 200 millimeter processes. This technology is similar to Rapid Thermal Processing and Plasma Enhanced Chemical Vapor Deposition systems. These systems employ a cold wall reactor, which minimizes film deposition on the chamber walls. Another important aspect of these systems is that they perform single-wafer processing. This eliminates the need to operate in surface reaction rate-limited regime, eliminates cross-batch process variability, does not suffer from gas depletion effects, and facilitates in-situ doping. The deposition conditions are different from batch reactors; a prime example would be polysilicon. They use higher operating pressures, which produce deposition rates that are a factor of ten higher than batch reactors. Furthermore, multiple chambers allows clustering. For example, one can process the entire gate stack in the tool, beginning with the gate pre-clean, followed by the gate oxidation-nitridation, followed by the in-situ doped polysilicon deposition.
These images show examples of the process chamber and the entire cluster tool for LPCVD. Although these tools are more complex and suffer from slower throughput, the benefits of performing multiple operations together and doing them more uniformly outweigh the disadvantages in most situations.
In conclusion, we discussed low pressure chemical vapor deposition. This technique is used primarily for silicon nitride and polysilicon deposition. We discussed the two types of reactors. There are batch, or hot wall, reactors, that allow 100 to 200 wafer to be processed simultaneously, and there are single wafer—or cold wall—reactors, that can be integrated into cluster tools for operations like gate stack processing. These single wafer systems also provide better control for uniformity and doping, which is essential in most advanced processes.
An important step for some types of Light Emitting Diodes (LEDs) is the substrate removal step. This is necessary for many types of vertical LED structures. There are two main techniques for performing this step: mechanical substrate removal and the laser lift-off technique. This approach fractures a horizontal interface, specifically the interface between the seimconductor and sapphire or silicon-carbide. This allows one to generate vertical and thin gallium nitride structures. Osram uses this approach for some of their products. IPG Photonics makes dedicated laser lift-off tools. Their manual tool can do 20 to 40 wafers per hour and their automated tool can do up to 60 wafers per hour. Their tools are relatively expensive though, ranging in price from $500,000 to $1,000,000.
Let’s look a little further into how the laser lift-off method works. First, one deposits metal on the receptor and semiconductor wafers. The typical metal is palladium on the receptor wafer, and titanium-palladium-indium on the semiconductor wafer. Second, one bonds the wafers together at low temperatures. This creates a palladium-indium alloy. Third, one focuses laser light through the semiconductor wafer on the sapphire/gallium nitride interface. The laser energy initiates a fracture, causing the gallium nitride layer to separate from the sapphire substrate, but remain attached to the receptor wafer due to the palladium-indium bond. This technique is growing in popularity, as it reduces the consumption of materials like sapphire substrates.
Q: I am just getting started in Semiconductor Reliability. What are the best conferences to attend that focus on this topic?
A: Depending on your location, there are several that I would recommend:
Please visit http://www.semitracks.com/courses/processing/cmos-bicmos-and-bipolar-process-integration.php to learn more about this exciting course!
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Failure and Yield Analysis on January 18-21, 2016 (Mon.-Thurs.) in San Jose, CA, USA
Packaging Failure and Yield Analysis on February 22-24, 2016 (Mon.-Wed.) in Manila, Philippines
Introduction to Processing on March 7-8, 2016 (Mon.-Tues.) in Shanghai, China
CMOS, BiCMOS and Bipolar Process Integration on March 21-22, 2016 (Mon.-Tues.) in Albuquerque, NM, USA
Wafer Fab Processing on March 29-April 1, 2016 (Tues.-Fri.) in San Jose, CA, USA
Failure and Yield Analysis on May 17-20, 2016 (Tues.-Fri.) in Munich, Germany
EOS, ESD and How to Differentiate on May 23-24, 2016 (Mon.-Tues.) in Munich, Germany
Semiconductor Reliability and Product Qualification on May 30-June 2, 2016 (Mon.-Thurs.) in Munich, Germany
Advanced Thermal Management and Packaging Materials on June 7-8, 2016 (Tues.-Wed.) in Albuquerque, NM, USA
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