Feature Article - Metal Issues Associated with Scaling - By Christopher Henderson

As chip technologies continue to scale, the aspect ratio of the metal lines and contacts becomes more challenging. As part of a recent effort, Semitracks has compiled information regarding the width, thickness, materials, and processing steps for the lowest metal layers in the upcoming 32 nm and 22 nm semiconductor technology nodes. The lowest metal layer (metal-1) constitutes the most difficult layer on the IC for probing and obtaining signal information. However, it is one of the most important layers to probe to ensure proper chip functionality and implementation.

At the 32 nm node, the industry is still planning to use tungsten contacts to silicon. The aspect ratio of the contact can be as high as 9-to-1. Although some are working to switch to a lined copper contact to silicon at 22 nm, this is not likely. To accommodate a 22 nm process, tungsten contacts need a scaled titanium nitride liner deposited by Atomic Layer Deposition (ALD) and a scaled tungsten ALD seed process, followed by tungsten Chemical Vapor Deposition (CVD) fill. Although logic devices may have high-aspect-ratio contacts (up to 9-to-1), the stacked capacitor DRAMs push the envelope for this process, with an aspect ratio approaching 20.

Several parameters correlate to the width and thicknesses of metal interconnect. The most critical parameter is resistance. The continued scaling of interconnect reduces the cross-sectional area of the metal, increasing its resistance. This resistance problem actually grows at a rate faster than the rate of scaling because of current limitations with barrier technology.

The extension of the copper/barrier structure to 22 nm will not be simple. The increasing resistance of copper at reduced cross-section, as well as grain boundary and surface scattering effects, will mean that the traditional Ta/TaN/ copper structure will likely not scale well to the 22 nm node with its 40 nm metal-1. To date, the industry has not figured out a method to scale the PVD TaN liner thinner than 8 nm. The other leading technique, ALD, does not produce an effective barrier because it does not adhere to copper. This is currently an area of significant work at leading edge manufacturers and equipment suppliers. Engineers are working on a dual material barrier that uses ALD TaN as the first layer, and then ruthenium (Ru) or RuN2 as the second layer. Copper does adhere to Ruthenium. Engineers are also pursuing silver-copper and silver-manganese alloys.

With ionized Physical Vapor Deposition (PVD) processes, the TaN barriers can be scaled to ~8 nm. ALD TaN does not adhere well to copper. Ruthenium is considered a good adhesion layer, though it is a poor copper barrier -- so a TaN or TiN barrier would still be required. If it is properly deposited, copper can be directly plated on ruthenium. There are many development efforts aimed at bringing a Ru/Cu-based interconnect into production. Both silver (Cu-Ag) and manganese (Cu-Mn) alloys are being considered for improved interconnect reliability. Upon annealing manganese, a self-forming MnO barrier with superior reliability forms. Both alloys have a small negative impact on resistivity.

Another critical parameter is capacitive coupling. Capacitive coupling affects both circuit operation and signal extraction. Researchers are reducing capacitive coupling through the use of dielectric materials with ever lower dielectric constants. To reduce interline capacitance, low-k materials with k in the 2.2–2.5 range will be integrated at the 22 nm node. These materials are likely to be porous low-k materials, such as Hydrogen Silsesquioxane (HSQ) and Methylsilsesquioxane (MSQ), or possibly a polymer dielectric, like cross-linked polyphenylene (SiLK) or Bis-benzocyclobutene (BCB).

Another alternative is air gap approaches, most of which involve thermal decomposition of a porogen material. Low-k materials are thermodynamically unstable and mechanically weak (the lower the dielectric constant, the weaker the material). Plasma damage is a big issue with porogen low-k dielectrics at 22 nm. Furthermore, porogen materials also suffer from water uptake. Scientists at NEC are working on a closed-pore material that may not need the barrier layers that porogens need for protection. Finally, integration with the assembly and packaging processes is critical with all these processes.

The image on the first page shows a likely scenario for the 32 and 22 nm nodes. In the past, the industry had working techniques and processes for nodes 2-3 generations ahead of current production. That is not the case anymore. The 22 nm node is only 2 generations away, and a number of the interconnect processes are still undetermined. It will be interesting to see how this transition unfolds.