Feature Article - Capacitance-Voltage Plotting, Part 2 - By Christopher Henderson

Continued from June’s Newsletter

Figure 3 helps to illustrate the MOS capacitance values that occur under different conditions. The positive charge resides at the metal-oxide interface, while the negative charge is distributed within the depletion region in the silicon. One can represent this as two capacitors in series. The capacitance across the oxide is straightforward to model, as it is simply the dielectric constant of the oxide divided by its thickness. To first order, the capacitance across the silicon is the dielectric constant of the silicon divided by the depletion width. According to capacitance behavior,

Therefore the total capacitance is given by

*To calculate the silicon capacitance at flatband, we need a method to approximate the capacitor plates in silicon. The first plate can simply be placed at the silicon surface. The second plate is placed at a depth equal to the Debye length, L sub D, which is given by

For p-type silicon, we can ignore n, the number of electrons in the material. The number of holes is primarily due to the number of acceptors in the material, so we can replace p with N_A. Therefore, in flatband, the silicon capacitance per unit area is simply the dielectric constant divided by the Debye length. One way to think about this is the Debye length is the distance over which carriers still feel disturbances.

So, to summarize our analysis of the high-frequency CV plot for an ideal MOS structure, there are three regions of interest: accumulation, depletion, and inversion. In strong accumulation, the majority carrier concentration increases rapidly at the surface, causing the Debye length to decrease and the capacitance in the silicon to increase. As the structure goes further into accumulation, the capacitance will increase to a maximum value around the capacitance of the oxide. As the magnitude of the accumulating voltage decreases, the majority carrier concentration decreases at the surface, causing the Debye length to increase and the capacitance in the silicon to decrease. In depletion, the depletion width increases, causing the capacitance in the silicon to decrease. It will continue to decrease below the flatband capacitance. In strong inversion, the inversion layer shields the sub-surface from the metal field lines, The depletion width saturates at X sub d max, the silicon capacitance at C sub silicon min, and the overall MOS capacitance at C sub min. It should be noted that the inversion layer forms only when the inversion carriers are provided by electron-hole pairs or injection from the junction.

Stay tuned for the conclusion of this article in August!