It has been known for some time that as VGS approaches VDS, hot carrier degradation increases in n-channel transistors with sufficiently short channel lengths, which is the case for most state-of-the-art ICs. The exact cause is uncertain, and can be attributed to various causes. One is the oxide field dependence of hydrogen bond breaking. A second is the increase in electron-electron scattering, and shift of the potential minimum to the silicon dioxide interface. A third is multi-vibrational excitation effects, which become important at high drain currents. And a fourth is localized self-heating in the drain region. Let’s assume electron-electron scattering dominates as an effect. The Damage Rate Is proportional to the difference between the drain current and the critical current, ICR raised to the power M times the interface trap density times the mass of the electron times the effective voltage. ICR is a critical or threshold current for the high VG effect, given by the equation in Figure 10.
This can be seen more clearly in graphical format. There is a peak that corresponds to the midpoint of the drain-to-source voltage as shown in Figure 11, predicted by the linear model. Notice the secondary peak at higher gate-to-source voltages that is predicted by the high V sub G model. Actually, the data indicate that both models play a role in the hot carrier behavior.
This leads to a unified model that can be used in the three regimes: low, medium and high gate-to-source voltages. Here we show the equations for each:
The total damage rate DR is then equal to the sum of the three individual regimes, and the change in current is also a function of the three changes in the resistance. IBM researchers call this the physical energy driven hot carrier model. It can be used in situations where more accuracy is required.
With scaling, the p-channel FET hot carrier behavior has evolved as well. It has gone from strong electron trapping over the low to mid Vg range and interface state generation at the higher Vg range, to weak electron trapping at the low Vg range, weak interface state generation at mid Vg, and a dominant high Vg mechanism. This high Vg mechanism has these characteristics. One, the time slope n is approximately 0.2 - 0.25 with slow measurements. Second, it is more dependent on VGS than VDS. And three, it is positively thermally activated. Interestingly, these are all characteristics of NBTI. We feel that this is no coincidence.
The graph in Figure 12 shows classical p-channel transistor behavior in older devices after hot carrier stressing. Notice that at low voltages electron trapping results in an increase in current, whereas at high voltages interface state generation and hole trapping result in a decrease in current.
In newer technologies, the effects are somewhat different. There is typically no increase in drain current at low stress voltages--indicating weak effects--but there is a more pronounced decrease in drain current due to some type of high gate voltage mechanism, as shown in Figure 13.
What exactly is the high gate voltage mechanism? It is thought to be an NBTI-enhanced effect by localized self heating. This is based on the idea that the effective temperature for NBTI is increased on the drain side of the channel due to carriers releasing energy there. Hot electrons generate acoustic phonons--or lattice vibrations-- which is in essence, heat generation. Also, hot electrons will generate optical phonons which in turn generate acoustic phonons or heat.
This is a model that captures this line of thinking. We start with the basic NBTI model, . The model is then generalized to the case of asymmetric, localized self heating by introducing an L term, and replacing T with TEFF. The parameters P, ΔH, and n remain the same. For the bulk region beneath the transistor, the self heating mechanism should contribute a ΔT proportional to PD, the local drain power dissipation. The Localized Self Heating Enhanced NBTI Model is then given by the expression with the parameters m ~ 1, θSH ~ 100-150 K/mW/µm. The parameter m is approximately equal to 1, and θSH, or the thermal diffusivity, is between 100 and 150 Kelvin per milliwatt per micron.
As we discussed previously, a major impact of hot electrons is the generation of interface states. The energetic electrons break the silicon-hydrogen bond, leaving a dangling silicon bond while the hydrogen diffuses away. This dangling bond will trap charge and also scatter charge carriers in the channel, affecting both the threshold voltage and the mobility of the transistor.
We want to leave you with these main ideas. Scaling associated and its effect on hot carriers is driven by energy, not electric field. The mid gate voltage regime--rather than the high gate voltage regime--is most representative of hot carrier behavior in typical CMOS switching applications for both n-channel and p-channel transistors. For a realistic assessment of product impact and the required timing margins, hot carrier effects should be characterized by the amount of parametric shift, not as an ambiguous lifetime parameter. The dominant device mechanism is typically hot carrier degradation for n-channel transistors, and NBTI for p-channel transistors. This may change with hi-K due to the effects of positive bias temperature instability or PBTI.
FinFET structures are quickly becoming common in advanced technologies. One important aspect of the fin is the taper angle. In general, process engineers try to design the fin with a taper angle as close to 90 degrees as possible. The image on the left shows a fin with a taper angle significantly less than 90 degrees, while the image on the right shows a structure with a taper angle close to 90 degrees.
A fin taper angle significantly less than 90 degrees leads to degraded short channel effects. The graph nearby shows the effect of fin taper angle on Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (SS). Notice that when the fin angle is less than 90 degrees, DIBL and SS increase. While these changes look fairly minor, they actually create more significant effects on transistor performance.
When we looks at the normalized drain current as a function of the gate bias, we see more pronounced effects. Notice that at moderate gate bias voltages of 0.4 - 0.6 volts, the normalized drain current is significantly less than 1.0. This effects the transistor not only at low VDS values, but also at higher VDS values.
Q: How does current-carrying-capability between Gold and Copper wire compare?
A: Both resistivity and melting temperature play a role in current-carrying-capability. Gold and Copper have somewhat different resistivities. Gold is 2.44e-6 ohm-cm, while Copper is 1.68e-6 ohm-cm. This means that Copper has about 1.4 times the current-carrying-capability of Gold. Gold and Copper have fairly similar melting temperatures, so melting temperature is not an important difference between the two metals.
Please visit http://www.semitracks.com/courses/packaging/mems-packaging-and-reliability.php to learn more about this exciting course!
(Click on each item for details).
Failure and Yield Analysis on August 10-13, 2015 (Mon.-Thurs.) in San Jose, CA, USA
Semiconductor Reliability on September 2-4, 2015 (Wed.-Fri.) in Munich, Germany
EOS, ESD and How to Differentiate on September 7-8, 2015 (Mon.-Tues.) in Munich, Germany
Product Qualification on September 9-10, 2015 (Wed.-Thurs.) in Munich, Germany
MEMS Packaging and Reliability on September 14-15, 2015 (Mon.-Tues.) in Boston, MA, USA
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at firstname.lastname@example.org.
To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (email@example.com).
We are always looking for ways to enhance our courses and educational materials.
Home > Newsletters > 2015 July Newsletter