Many times when I discuss training with customers, I bring up the idea of e-learning. The responses I get are often interesting, and I thought it would be good to address some of these in our newsletter. Over the next three issues I will address the positive aspects of e-learning, the negative aspects, and then address some concerns that people voice.
Next month, we will discuss the negative aspects of e- learning.
Activity in package design and package materials development is probably greater now than at any time during the history of the development of the integrated circuit. In the 1960s and 1970s, ceramic packages were quite common and were available in a limited number of formats, like dual inline packages (DIPS), flat packs, and transistor outline (TO) formats. As the use of electronics grew and new form factors and environment profiles appeared, package format proliferated. Both the plastic package and the hybrid microcircuit were introduced in the 70s. By the 1980s, new technologies like tape automated bonding (TAB) allowed for more packaging formats. More complex devices demanded higher pin count packages, and formats like the pin grid array (PGA) and ball grid array (BGA) appeared. The consumer electronics revolution helped bring about the transition to surface mount technology and packaging. The mobile electronics world helped to bring about chip scale packaging (CSP) and wafer level scale packaging (WLCSP).
In many of today’s applications, the package is integral to functionality. For example, CMOS sensor chips in cameras and microcontroller chips in RF ID tags and smartcards require unique packaging technologies. As the world of electronics pushes deeper into all areas of sensing and information processing, newer package types are being developed for biological, industrial, and energy uses. Laboratories on a chip, solid- state lighting, and medical electronics are driving many of today’s innovations in packaging. For high performance, lightweight electronics, the ultimate goal is 3-dimensional integration. Technologies like through silicon vias, optical interconnections and RF signal coupling are now important areas of research.
Q: What are the standard practices for implementing 2nd level qual?
A: Qualification requirements vary considerably by package, application conditions, and lifetime requirements. There is a balance between a standard set of requirements and those targeted at a specific customer’s need. The trends have been re-use of existing data based on structural similarity and failure mechanism-based testing, so we do the tests that are most likely to catch the failure mechanisms we expect based on FMEA analysis. As a result, we need to become experts in failure mechanisms.
Second level tests relate to attachment, and are defined by JEDEC specs JESD122 -B105 (Fatigue) B104 (Shock) B103 (Vibration) etc., and may include bending, twisting, etc. Your customer may have some specific application-related issues. The application board construction, layout, materials, and processing are critical elements. However, on the IC supplier side, standard boards must be used, typically with a board layout designed to be testable (Daisy Chain), diagnosable, and sometimes capable of using Event Detection (continuous monitoring hardware).
Structural similarity is used to determine how much existing data can be used to qualify a new product/package, process, or part in a new application. Qualifying a device requires knowing what factors are important. Historically, this was formalized in CPCN (Critical Process Change Notifications) and usually required custom qualification. By applying structural similarity rules, the same reliability assurances can be achieved faster and cheaper. The process should be defined in a company’s qualification standards and qualification reports based on structural similarity should state the justification why that data is applicable. Knowledge is required both to make the right decisions and to document that decision to the (potential) customer.
So how do you determine the rules for structural similarity in order to decide when qualification data from one product can be re-used to qualify a different product? First, you must know the important failure mechanisms and what factors make them worse or better, preferably using some model. Obtaining this data requires reliability stressing to failure and failure analysis to determine root cause and causative factors. Normally, the stressing uses test chips test boards, serial connected pins optimized for simple stressing and analysis. Results can be used to calibrate the reliability models, including finite element analysis. Internal data is preferred. Although published data can also be used, the details can be sketchy. Not all knowledge comes from these test vehicles.
Any failure in stress or field use can offer insight into the failure cause. Out of this knowledge, some general rules can be developed. For example, below are some general observations for cyclic fatigue testing that might guide structural similarity rules. With more specific data, the rules could be made more specific.
Gull-wing parts: not much concern about solder fatigue for normal commercial applications, nor for drop test. By design, these failures are not worst case. Something else will fail first.
Substrate package fatigue: larger packages are worse, smaller solder volume is worse, finer pitch is worse, partially populated ball location can be critically layout dependent. Less important are wires, die stack, chip coat.
Leadless: similar to substrate packages
PackageLess (e.g. WLCSP): here foundry, process, technology node, UBM and materials are the main factors.
Board factors: can be even more critical - for example, clamping of boards at the edge is bad. Components near large features can be a problem; thicker substrates are usually better. These, however, are outside the control of the IC vendor.
Please visit http://www.semitracks.com/courses/technology/biotechnology-for-electrical-engineers.php to learn more about this exciting course!
(Click on each item for details).
Photovoltaics Overview on July 12, 2010 in San Francisco, CA, USA
Photovoltaics Technology and Manufacturing on July 13, 2010 in San Francisco, CA, USA
Reliability and Characterization Challenges on July 15, 2010 in San Francisco, CA, USA
Wafer Fab Processing on August 9-12, 2010 in San Jose, CA, USA
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