Capacitance-voltage or CV plotting, is a common electrical technique for investigating charge phenomena in MOS structures and transistors. In this article, we’ll review some of the characteristics of the CV plot, and how it is used to identify and characterize yield and process integration problems.
Figure 1 shows a high and low-frequency capacitance-voltage plot of an ideal MOS structure. The high frequency curve is denoted by the solid line, while the low frequency curve is denoted by the dashed line. The capacitance is high when the structure is in accumulation, decreases toward the flatband condition at zero volts applied to the structure, and decreases further toward Cmin, the steady state high frequency condition. In the low frequency condition, the capacitance begins to rise again at a voltage called the match point. As the voltage increases, the capacitance increases to a level similar to that in accumulation. This is sometimes referred to as a quasi-static CV measurement, and is measured using the voltage ramp method. In the voltage ramp method, the voltage is ramped very slowly at a given rate, typically less than 50 mV/sec. The measured displacement current is proportional to the capacitance. The frequency is considered to be low when the generation of electron-hole pairs keep up with the signal. When the frequency is high, only majority carriers can follow the signal. At low frequencies, the charge exchange with the inversion minority carriers is in step with the varying signal. The small signal response dQ to dV appears at the surface (inversion) rather that at the depletion boundary. As the inversion layer forms, the capacitance increases back to Cmax ≈ Cox.
Figure 2 shows a high-frequency capacitance-voltage, or CV plot of an ideal MOS structure. High frequency measurements allow the user to hide the effects of minority carriers since minority carriers cannot react fast enough to follow the signal. The capacitance is high, approximately that of the ideal capacitance across the oxide, when the voltage is negative. When the voltage is negative, the MOS structure is in accumulation so the surface hole concentration increases, raising the capacitance. At flatband, the capacitance should be equal to the ideal capacitance for the flatband condition. As the voltage goes positive, the MOS structure goes into depletion. The surface electron concentration increases, but remains at a level too low to offset the decrease in surface hole concentration. In weak inversion, the surface electron hole concentration is higher than the surface hole concentration, but the depletion width increases, lowering the capacitance further. In strong inversion, the surface electron concentration equals the surface hole concentration at flatband, and the depletion width reaches its maximum. The capacitance reaches its minimum at this value as well. This is also the threshold voltage point, where Ψs is approximately equal to 2Φb. The steady-state condition is reached when sufficient electrons are supplied to the surface mechanisms like electron-hole pair generation.
There is currently a lot of research and development work on Through-Silicon Vias or TSVs. Although polysilicon in the TSV makes for a good material from the standpoint of a good thermal match, manufacturers would prefer to use copper, since it has a much lower resistance. Copper has a much higher coefficient of thermal expansion than silicon, leading to several failure mechanisms. A common failure mechanism is a phenomenon called copper pumping. During thermal cycling the copper expands and contracts, alternately pressing up on the back end of the line (BEOL) materials, and relaxing back. This creates the bulge seen in this image. This pumping action causes stress in the BEOL layers, leading to BEOL damage, or cracking in the metal and dielectric layers. Most process engineers work to reduce the copper pumping effect through the use of annealing and sintering. These steps increase grain size and reduce the coefficient of thermal expansion somewhat.
Q: How can I limit the breakdown damage when an oxide is stressed in a Power MOSFET device?
A: Use a current limiting resistor or set a lower compliance limit on the SMU. A more active monitoring circuit may be needed if the FN tunneling current is already significant.
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EOS in Manufacturing on June 28, 2011 - Online
ESD Design and Technology on July 10-12, 2011 in Tel Aviv, Israel
ESD Design and Technology on August 23-25, 2011 in San Jose, CA, USA
IC Packaging Metallurgy on September 12-13, 2011 in Munich, Germany
Wafer Fab Processing on September 26-29, 2011 in Singapore
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