One useful technique to indirectly observe the damage created by hot carriers is to measure the p-well current. The p-well current closely tracks the current into the gate oxide in a hot carrier stress situation. In this graph, one can see that the p-well current peaks at approximately 50% of the drain-to-source voltage. The p-well current is almost non-existent at low gate-to-source voltages, increases rapidly to its peak, and then tails off to a lower value at higher gate-to-source voltages. At low gate-to-source voltages, there is no current through the channel. At high gate-to-source values the pinch-off region decreases, precluding the possibility of electrons scattering into the p-well. The p-well current at these higher values comes solely from diffusion currents.
In Figure 8, we overlay a plot of light emission intensity with the p-well current. One can see that the light emission and the p-well current track fairly closely. There are some minor differences that occur because of the behavior of the transistor, but to first order they are the same. This means that p-well current is an excellent indicator of hot carrier damage. Engineers can therefore ascertain the level of hot electron damage by monitoring the p-well current. This electrical test is cost effective and straightforward to perform on a test structure. In contrast, a direct measurement of the light intensity requires sophisticated night vision camera or CCD hardware.
Although light emission is an expensive and more complicated test, it can be an invaluable tool for localizing hot carrier damage, especially if one does not know where it might be occurring. In Figure 9 one can see light emission occurring in the n-channel transistors associated with the ring oscillator, and the input and output buffers to the test structure. A ring oscillator provides a worst-case scenario for digital logic, since it is running at the maximum frequency of the technology.
Classical hot carrier modeling is done using the equation Δp = Atn. Generally, one can describe the degradation as a change in a parameter, Δp. Δp is equal to A times t raised to the power n, where t represents time, A is a material dependent parameter, and n is an empirically determined exponent.
For more detailed calculations, one can model the n- and p-channel transistors separately. One uses the Eyring model for n-channel transistors, where the time to failure is given by the equation TTF = B(Isub)-Ne(EA/kT). B is an arbitrary scale factor, Isub in the peak substrate current during stressing. N is a current exponent that is typically between 2 and 4, and EA is the activation energy. Please note that the apparent activation energy can be negative or positive depending on channel length and voltage.
One can use the Eyring model for p-channel transistors as well. This model was developed for transistors with gate lengths greater than a quarter micron, and is given by the equation TTF = B(Igate)-Me(EA/kT). Again, B is an arbitrary scale factor. Igate is the peak gate current during stressing. M is the current exponent, and EA is the activation energy, which is typically close to zero. One should note that a rough “rule-of-thumb” for the gate current versus voltage dependence of P-channel devices is that the peak gate current doubles for each 0.5 V increase in source-drain voltage.
The typical model for p-channel devices that have gate lengths of less than a quarter micron is TTF = B(Isub)-Ne(EA/kT). The equation is similar to the long channel equation, except that substrate current is used instead of gate current. Please note that the apparent activation energy can be negative or positive depending on channel length and voltage.
Here we will work an example problem where we calculate the acceleration factor (AF, relative severity) for hot carrier injection for an office environment versus a stressed test structure environment. We assume the office = 50°C chip temperature & substrate current of 1µA and the test structure environment conditions are -40°C & 10µA substrate current (accelerated by elevating Vc) and assume a current exponent (N) of 3 and an activation energy of minus 0.15 electron-volts. The conclusion is that moving from accelerated test structure environment to the office environment will increase the time to fail value to by 8000 X of the accelerated stress value, of which 1000 X is due to substrate current and 8 X is due to temperature.
Scientists studying hot carrier degradation have identified various mechanisms associated with n-channel and p-channel transistors. In n-channel transistors, hot electrons tend to generate interface states when the gate voltage is between 33 and 50% of the drain-to-source voltage. When the gate voltage is approximately 20% of the drain-to-source voltage, hole injection dominates the process. As the gate voltage approaches the drain-to-source voltage, electron injection dominates the process. In p-channel transistors, oxide electron trapping dominates a lower gate voltage, say 20% of the drain-to-source voltage. At higher gate voltages of 33 to 50% of the drain-to-source voltage, interface state generation dominates.
In a standard build-up package, there is a core material made from FR4 or BT epoxy laminate. A build-up package requires a fan-out region to match the bump and/or the line pitch to the plated through hole pitch. We highlight this region with the yellow ellipses in Figure 1. In a coreless package there is no core material, just build-up materials. This facilitates direct signaling. Designers can use all of the layers for signals, and the approach maximizes wiring efficiency. It also reduces impedance mismatches that occur as the result of the plated-through holes. Co-planarity is also better with a coreless package. The major issue with coreless substrates is warpage. Warpage is up to four times worse with a coreless substrate due to the lack of a rigid core to hold everything in place. As a result, not many manufacturers are using coreless substrates. However, Sony uses this technology in the latest version of their Cell processor family.
The major player for coreless package build-up materials is Ajinomoto. The Ajinomoto Build-up Film--or ABF--is used extensively in the industry already on substrates with cores, and now used for coreless build-up as well (see Figure 2).
ABF is a three-layer polymer system, with a polyethylene terephthalate (PET) support film, a resin layer, and a cover film (see Figure 3). One can deposit copper on the thin to create interconnect traces. Ajinomoto has evolved its ABF to remove the halogens, lower the coefficient of thermal expansion, and allow for narrower vias. It is used widely as a standard build-up material, and is now in limited use for coreless substrates.
Q: How fast does an underfill flow around the bumps or pillars on a device?
A: There are a number of variables involved in determining that number. They include: the viscosity of the underfill (which is dependent on the epoxy properties and the amount of filler particles), the size of the package, the number of bumps, the density of bumps (which is a function of their pitch), the height of the bumps, the temperature, other chemicals present (like adhesion promoters and flux), and so on. As a rough number though, a combination of substrate temperature, material, equipment and dispense process can show complete flow out under a 25mm square die with 60um gap in about 35 seconds.
Please visit http://www.semitracks.com/courses/packaging/mems-packaging-and-reliability.php to learn more about this exciting course!
(Click on each item for details).
Failure and Yield Analysis on August 10-13, 2015 (Mon.-Thurs.) in San Jose, CA, USA
Semiconductor Reliability on September 2-4, 2015 (Wed.-Fri.) in Munich, Germany
EOS, ESD and How to Differentiate on September 7-8, 2015 (Mon.-Tues.) in Munich, Germany
Product Qualification on September 9-10, 2015 (Wed.-Thurs.) in Munich, Germany
MEMS Packaging and Reliability on September 14-15, 2015 (Mon.-Tues.) in Boston, MA, USA
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